120A. The hard mask layer can be formed utilizing a deposition process including, but not limited to, CVD, PECVD, ALD, physical vapor deposition (PVD) or sputtering.

A photoresist material (not depicted) is then deposited onto the surface of the hard mask layer. The photoresist material can be applied by any suitable techniques, including, but not limited to, coating or spin-on techniques. A photomask (not depicted) patterned with shapes defining line openings 121A, 123A, 125A to be formed is placed over the photoresist material, and the photomask pattern is transferred to the photoresist material using a lithographic process, which creates recesses in the uncovered regions of the photoresist material. The resulting patterned photoresist material is subsequently used to create the same pattern in the hard mask layer. Dry etch techniques (for example, an anisotropic etch process, such as reactive ion etch) may be employed to selectively remove portions of the hard mask layer to form the patterned hard mask. After formation of the patterned hard mask, the photoresist material may be stripped from the patterned hard mask by ashing or other suitable processes. The resulting structure may be subjected to a wet clean.

The resulting patterned hard mask, which acts as an etch mask, is formed such that the portions of the underlying dielectric layer 120A corresponding to line openings 121A, 123A, 125A to be formed are protected by the patterned hard mask, while the remaining portions of the underlying dielectric layer 120A are left exposed. During patterning of dielectric layer 120A using the patterned hard mask, the physically exposed portions of dielectric layer 120A are removed by an anisotropic etching process such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching to form the first set of low aspect ratio line openings 121A, 123A, 125A.

FIG. 1C illustrates a cross-sectional view of semiconductor structure 100B depicted in FIG. 1B after performing subsequent processing steps, generally designated 100C, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 100C, a metal liner material is conformally deposited onto the exposed surfaces of the patterned dielectric layer 120A, a conductive metal material is deposited within and filling the first set of low aspect ratio line openings 121A, 123A, 125A (depicted in FIG. 1B), followed by a planarization process to form a first set of low aspect ratio line segments 131A, 133A, 135A.

After patterning dielectric layer 120A, a metal barrier material is conformally deposited onto the exposed surfaces of the patterned dielectric layer 120A to form a barrier layer 140A. Barrier layer 140A may include one or more thin layers of material such as, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (HfN), cobalt (Co), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium-tungsten (TiW), tungsten nitride (WN) manganese (Mn), manganese nitride (MnN) or other barrier materials (or combinations of barrier materials) such as RuTaN, Ta/TaN, CoWP, NiMoP, or NiMoB which are suitable for the given application. The thin metal barrier serves as a barrier diffusion layer and adhesion layer. A conformal layer of a metal barrier material may be deposited using known techniques including, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition or plating. The thickness of barrier layer 140A may vary depending on the deposition process used, as well as the material employed. In some embodiments, barrier layer 140A may have a thickness from 2 nm to 50 nm. However, other thicknesses that are less than 2 nm, or greater than 50 nm can also be employed in embodiments of the present invention.

After forming barrier layer 140A, a conductive metal layer 150A is formed by depositing (e.g., via atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any other suitable deposition techniques) a conductive metal material within and filling line openings 121A, 123A, 125A of the patterned dielectric layer 120A. In an embodiment, the conductive metal material may be a metal or metal alloy including, but not limited to, copper (Cu), aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), nickel (Ni), or an alloy thereof, such as, for example, a Cu—Al alloy.

A planarization process such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may subsequently be performed to remove portions of barrier layer 140A and conductive metal layer 150A located above the top surface of dielectric layer 120A. The planarization stops at the top surface of dielectric layer 120A, such that the top surface of the first set of low aspect ratio line segments 131A, 133A, 135A is substantially coplanar with the top surface dielectric layer 120A.

FIG. 1D illustrates a cross-sectional view of semiconductor structure 100C depicted in FIG. 1C after performing subsequent processing steps, generally designated 100D, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 100D, a dielectric material is selectively deposited onto the top surface dielectric layer 120A to form a dielectric layer 120B having a second set of low aspect ratio line openings 121B, 123B, 125B. As depicted by FIG. 1D, the second set of low aspect ratio line openings 121B, 123B, 125B are formed above and in vertical alignment with the first set of low aspect ratio line segments 131A, 133A, 135A, respectively.

In forming dielectric layer 120B, a dielectric material that is selective to the material(s) of dielectric layer 120A over the material(s) of barrier layer 140A and conductive metal layer 150A is deposited (e.g., via selective atomic layer deposition (ALD), selective chemical vapor deposition (CVD) or any other suitable deposition techniques) onto the top surface of dielectric layer 120A. Dielectric layer 120B may be formed using any material(s) that are selective to the material(s) of dielectric layer 120A over the material(s) of barrier layer 140A and conductive metal layer 150A. For example, if dielectric layer 120A is formed from SiCOH, barrier layer 140A is formed from TaN, and conductive metal layer 150A is formed from copper (Cu), parylene may be used to form dielectric layer 120B since parylene is selective to SiCOH over TaN and Cu. In some embodiments, and as depicted by FIG. 1D, dielectric layer 120B and dielectric layer 120A are formed from different materials. In other embodiments, dielectric layer 120B and dielectric layer 120A are formed from the same material(s).

FIG. 1E illustrates a cross-sectional view of semiconductor structure 100D depicted in FIG. 1D after performing subsequent processing steps, generally designated 100E, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 100E, a metal barrier material is selectively and conformally deposited onto the exposed surfaces of the patterned dielectric layer 120B, a conductive metal material is deposited within and filling the second set of low aspect ratio line openings 121B, 123B, 125B (depicted in FIG. 1D), followed by a planarization process to form a second set of low aspect ratio line segments 131B, 133B, 135B. As depicted by FIG. 1E, the second set of low aspect ratio line segments 131B, 133B, 135B are in contact and in vertical alignment with the first set of low aspect ratio line segments 131A, 133A, 135A, respectively.

After forming dielectric layer 120B, a metal barrier material is conformally and selectively deposited onto the exposed surfaces of the patterned dielectric layer 120B to form a barrier layer 140B. In forming barrier layer 140B, a metal barrier material that is selective to the material(s) of dielectric layer 120B over the material(s) of conductive metal layer 150A is deposited (e.g., via selective atomic layer deposition (ALD), selective chemical vapor deposition (CVD) or any other suitable deposition techniques) onto the top surface of dielectric layer 120B. Barrier layer 140B may be formed using any material(s), including, but not limited to those listed above with respect to barrier 140A, that are selective to the material(s) of dielectric layer 120B over the material(s) of conductive metal layer 150A. For example, if dielectric layer 120B is formed from parylene and conductive metal layer 150A is formed from copper (Cu), TaN may be used to form barrier layer 140B since TaN is selective to parylene over Cu. In some embodiments, and as depicted by FIG. 1E, barrier layer 140B and barrier layer 140A are formed from different materials. In other embodiments, barrier layer 140B and barrier layer 140A are formed from the same material(s).

A conductive metal layer 150B is then formed by depositing (e.g., via atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any other suitable deposition techniques) a conductive metal material within and filling line openings 121B, 123B, 125B of the patterned dielectric layer 120B. In an embodiment, the conductive metal material may be a metal or metal alloy including, but not limited to, copper (Cu), aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), nickel (Ni), or an alloy thereof, such as, for example, a Cu—Al alloy. In some embodiments, and as depicted by FIG. 1E, conductive metal layer 150B and conductive metal layer 150A are formed from the same material(s). In other embodiments, conductive metal layer 150B and conductive metal layer 150A are formed from different materials.

A planarization process such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may subsequently be performed to remove portions of barrier layer 140B and conductive metal layer 150B located above the top surface of dielectric layer 120B.

The planarization stops at the top surface of dielectric layer 120B, such that the top surface of the second set of low aspect ratio line segments 131B, 133B, 135B is substantially coplanar with the top surface dielectric layer 120B.

FIG. 1F illustrates a cross-sectional view of semiconductor structure 100E depicted in FIG. 1E after performing subsequent processing steps, generally designated 100F, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 100F, a dielectric material is selectively deposited onto the top surface of dielectric layer 120B to form a dielectric layer 120C having a third set of low aspect ratio line openings 121C, 123C, 125C. As depicted by FIG. 1F, the third set of low aspect ratio line openings 121C, 123C, 125C are formed above and in vertical alignment with the second set of low aspect ratio line segments 131B, 133B, 135B, respectively.

In forming dielectric layer 120C, a dielectric material that is selective to the material(s) of dielectric layer 120B over the material(s) of barrier layer 140B and conductive metal layer 150B is deposited (e.g., via selective atomic layer deposition (ALD), selective chemical vapor deposition (CVD) or any other suitable deposition techniques) onto the top surface of dielectric layer 120B. Dielectric layer 120C may be formed using any material(s) including, but not limited, to those listed above with respect to dielectric layer 120A, that are selective to the material(s) of dielectric layer 120B over the material(s) of barrier layer 140B and conductive metal layer 150B. In some embodiments, and as depicted by FIG. 1F, dielectric layer 120C and dielectric layer 120B are formed from the same materials. In other embodiments, dielectric layer 120C and dielectric layer 120B are formed from different materials.

FIG. 1G illustrates a cross-sectional view of semiconductor structure 100F depicted in FIG. 1F after performing subsequent processing steps, generally designated 100G, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 100G, a metal barrier material is selectively and conformally deposited onto the exposed surfaces of the patterned dielectric layer 120C, a conductive metal material is deposited within and filling the third set of low aspect ratio line openings 121C, 123C, 125C (depicted in FIG. 1E), followed by a planarization process to form a third set of low aspect ratio line segments 131C, 133C, 135C. As depicted by FIG. 1E, the third set of low aspect ratio line segments 131C, 133C, 135C are in contact and in vertical alignment with the second set of low aspect ratio line segments 131B, 133B, 135B, respectively.

After forming dielectric layer 120C, a metal barrier material is conformally and selectively deposited onto the exposed surfaces of the patterned dielectric layer 120C to form a barrier layer 140C. In forming barrier layer 140C, a metal barrier material that is selective to the material(s) of dielectric layer 120C over the material(s) of conductive metal layer 150B is deposited (e.g., via selective atomic layer deposition (ALD), selective chemical vapor deposition (CVD) or any other suitable deposition techniques) onto the top surface of dielectric layer 120C. Barrier layer 140C may be formed using any material(s), including, but not limited to those listed above with respect to barrier 140A, that are selective to the material(s) of dielectric layer 120C over the material(s) of conductive metal layer 150B. In some embodiments, and as depicted by FIG. 1E, barrier layer 140C and barrier layer 140B are formed from the same materials. In other embodiments, barrier layer 140C and barrier layer 140B are formed from different material(s).

A conductive metal layer 150C is then formed by depositing (e.g., via atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any other suitable deposition techniques) a conductive metal material within and filling line openings 121C, 123C, 125C of the patterned dielectric layer 120C. In an embodiment, the conductive metal material may be a metal or metal alloy including, but not limited to, copper (Cu), aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), nickel (Ni), or an alloy thereof, such as, for example, a Cu—Al alloy. In some embodiments, and as depicted by FIG. 1E, conductive metal layer 150C and conductive metal layer 150B are formed from the same material(s). In other embodiments, conductive metal layer 150C and conductive metal layer 150B are formed from different materials.

A planarization process such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may subsequently be performed to remove portions of barrier layer 140C and conductive metal layer 150C located above the top surface of dielectric layer 120C. The planarization stops at the top surface of dielectric layer 120C, such that the top surface of the third set of low aspect ratio line segments 131C, 133C, 135C is substantially coplanar with the top surface dielectric layer 120C.

As depicted by FIG. 1G, a plurality of high aspect ratio metal lines that are substantially uniform in height and width are formed from multiple low aspect ratio line segments. A first high aspect ratio metal line 161 is formed from low aspect ratio line segments 131A, 131B, and 131C. A second high aspect ratio metal line 163 is formed from low aspect ratio line segments 133A, 133B, and 133C. A third high aspect ratio metal line 165 is formed from low aspect ratio line segments 135A, 135B, and 135C. Although first, second, and third high aspect ratio metal lines 161, 163, 165 are depicted as being formed from three low aspect ratio line segments, embodiments of the present invention are not limited to high aspect ratio metal lines formed from three low aspect ratio line segments. Rather, embodiments of the present invention may contemplate high aspect ratio metal lines formed from more or less than three low aspect ratio line segments. In an embodiment, high aspect ratio metal lines are formed from at least two low aspect ratio line segments. The total number of low aspect ratio lines segments used to form a single high aspect ratio metal line may vary depending on the desired height of the high aspect ratio lines of the interconnect structure. In an embodiment, the pitch between first and second high aspect ratio metal lines, and the pitch between second and third high aspect ratio metal lines is less than 30 nanometers. In an embodiment, the pitch between first and second high aspect ratio metal lines 161, 163, and the pitch between second and third high aspect ratio metal lines 163, 165, is less than 30 nanometers. In an embodiment, the pitch between first and second high aspect ratio metal lines 161, 163, and the pitch between second and third high aspect ratio metal lines 163, 165, is greater than or equal to 30 nanometers.

FIG. 2A illustrates a cross-sectional view of an initial semiconductor structure, generally designated 200A, in accordance with at least one embodiment of the present invention. It should be noted that semiconductor structure 200A is equivalent to semiconductor structure 100D depicted in FIG. 1D. Accordingly, semiconductor structure 200A may be formed from the same processes and materials as described above with reference to semiconductor structures 100A, 100B, 100C, and 100D of FIGS. 1A, 1B, 1C, and 1D, respectively.

As depicted by FIG. 2A, semiconductor structure 200A includes dielectric layer 120A formed on substrate 110. After patterning dielectric layer 120A to form the first set of low aspect ratio line openings 121A, 123A, 125A (depicted in FIG. 1B), metal barrier 140A was formed by depositing a metal barrier material on the exposed surfaces of the patterned dielectric layer 120A, conductive metal layer 150A was formed by depositing a conductive metal material within and filling the first set of low aspect ratio line openings 121A, 123A, 125A, a planarization process was performed to remove portions of barrier layer 140A and conductive metal layer 150A located above the top surface of dielectric layer 120A to form first set of low aspect line segments 131A, 133A, 135A. Thereafter, a second set of low aspect line openings 121B, 123B, 125B were formed in dielectric layer 120B by selectively depositing a dielectric material onto the top surface of dielectric layer 120A.

FIG. 2B illustrates a cross-sectional view of semiconductor structure 200A depicted in FIG. 2A after performing subsequent processing steps, generally designated 200B, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 200B, a metal barrier material is formed.

Barrier layer 240B may be formed by conformally depositing a metal barrier material (e.g., via atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any other suitable deposition techniques) onto the exposed surfaces of the patterned dielectric layer 120B and conductive metal layer 150A. Barrier layer 240B may be formed using material(s) including, but not limited to, those listed above with respect to barrier 140A. In some embodiments, and as depicted by FIG. 2B, barrier layer 240B and barrier layer 140A are formed from the same material(s). In other embodiments, barrier layer 240B and barrier layer 140A are formed from different materials.

FIG. 2C illustrates a cross-sectional view of semiconductor structure 200B depicted in FIG. 2B after performing subsequent processing steps, generally designated 200C, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 200C, portions of barrier layer 240B previously formed on the top surfaces of dielectric layer 120B and conductive metal layer 150A are removed by an anisotropic etching process such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching.

FIG. 2D illustrates a cross-sectional view of semiconductor structure 200C depicted in FIG. 2C after performing subsequent processing steps, generally designated 200D, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 200D, a conductive metal layer 250B is formed by depositing a conductive metal material within and filling the second set of low aspect ratio line openings 121B, 123B, 125B (depicted in FIG. 2C), followed by a planarization process to form a second set of low aspect ratio line segments 231B, 233B, 235B. As depicted by FIG. 2D, second set of low aspect ratio line segments 231B, 233B, 235 are in contact and in vertical alignment with the first set of low aspect ratio line segments 131A, 133A, 135A, respectively.

Conductive metal layer 250B may be formed from the same processes and materials as described above with reference to conductive metal layer 140A. In some embodiments, and as depicted by FIG. 2D, conductive metal layer 250B and conductive metal layer 150A are formed from the same material(s). In other embodiments, conductive metal layer 250B and conductive metal layer 150A are formed from different materials.

FIG. 2E illustrates a cross-sectional view of semiconductor structure 200D depicted in FIG. 2D after performing subsequent processing steps, generally designated 200E, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 200E, a dielectric material is selectively deposited onto the top surface of dielectric layer 220B to form a dielectric layer 220C having a third set of low aspect ratio line openings 221C, 223C, 225C. As depicted by FIG. 2E, the third set of low aspect ratio line openings 221C, 223C, 225C are formed above and in vertical alignment with the second set of low aspect ratio line segments 231B, 233B, 235B, respectively.

In forming dielectric layer 220C, a dielectric material that is selective to the material(s) of dielectric layer 220B over the material(s) of barrier layer 240B and conductive metal layer 250B is deposited (e.g., via selective atomic layer deposition (ALD), selective chemical vapor deposition (CVD) or any other suitable deposition techniques) onto the top surface of dielectric layer 220B. Dielectric layer 220C may be formed using any material(s) including, but not limited, to those listed above with respect to dielectric layer 120A, that are selective to the material(s) of dielectric layer 220B over the material(s) of barrier layer 240B and conductive metal layer 150B. In some embodiments, and as depicted by FIG. 2E, dielectric layer 220C and dielectric layer 220B are formed from the same materials. In other embodiments, dielectric layer 220C and dielectric layer 220B are formed from different materials.

FIG. 2F illustrates a cross-sectional view of semiconductor structure 200E depicted in FIG. 2E after performing subsequent processing steps, generally designated 200F, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 200F, a metal barrier material is deposited to form a barrier layer 240C.

Barrier layer 240C may be formed by conformally depositing a metal barrier material (e.g., via atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any other suitable deposition techniques) onto the exposed surfaces of the patterned dielectric layer 220C, barrier layer 240B, and conductive metal layer 250B. Barrier layer 240C may be formed using material(s) including, but not limited to, those listed above with respect to barrier 140A. In some embodiments, and as depicted by FIG. 2F, barrier layer 240C and barrier layer 240B are formed from the same material(s). In other embodiments, barrier layer 240C and barrier layer 240B are formed from different materials.

FIG. 2G illustrates a cross-sectional view of semiconductor structure 200F depicted in FIG. 2F after performing subsequent processing steps, generally designated 200G, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 200G, portions of barrier layer 240C previously formed on the top surfaces of dielectric layer 220C and conductive metal layer 250B are removed by an anisotropic etching process such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching.

FIG. 2H illustrates a cross-sectional view of semiconductor structure 200G depicted in FIG. 2G after performing subsequent processing steps, generally designated 200H, in accordance with at least one embodiment of the present invention. In assembly of semiconductor structure 200H, a conductive metal layer 250C is formed by depositing a conductive metal material within and filling the third set of low aspect ratio line openings 221C, 223C, 225C (depicted in FIG. 2G), followed by a planarization process to form a third set of low aspect ratio line segments 231C, 233C, 235C. As depicted by FIG. 2H, the third set of low aspect ratio line segments 231C, 233C, 235C are in contact and in vertical alignment with the second set of low aspect ratio line segments 231B, 233B, 235B, respectively.

Conductive metal layer 250C may be formed from the same processes and materials as described above with reference to conductive metal layer 150A. In some embodiments, and as depicted by FIG. 2H, conductive metal layer 250C and conductive metal layer 250B are formed from the same material(s). In other embodiments, conductive metal layer 250C and conductive metal layer 250B are formed from different materials.

As depicted by FIG. 2H, a plurality of high aspect ratio metal lines that are substantially uniform in height and width are formed from multiple low aspect ratio line segments. A first high aspect ratio metal line 261 is formed from low aspect ratio line segments 131A, 131B, and 231C. A second high aspect ratio metal line 263 is formed from low aspect ratio line segments 133A, 133B, and 233C. A third high aspect ratio metal line 265 is formed from low aspect ratio line segments 135A, 135B, and 235C. Although first, second, and third high aspect ratio metal lines 261, 263, 265 are depicted as being formed from three low aspect ratio line segments, embodiments of the present invention are not limited to high aspect ratio metal lines formed from three low aspect ratio line segments. Rather, embodiments of the present invention may contemplate high aspect ratio metal lines formed from more or less than three low aspect ratio line segments. In an embodiment, high aspect ratio metal lines are formed from at least two low aspect ratio line segments. The total number of low aspect ratio lines segments used to form a single high aspect ratio metal line may vary depending on the desired height of the high aspect ratio lines of the interconnect structure. In an embodiment, the pitch between first and second high aspect ratio metal lines