FIG. 13) the same as that of individual trenches 40U/40L. A masking material 82 may be used and remain above insulator material 80 at this point of the processing, as shown. Masking material 82 may or may not be sacrificial, with photoresist being but one sacrificial example.

Referring to FIGS. 15-17, conductive plugs 84 (not shown) and uppermost portions of channel material 36 have been removed from trenches 40U, for example by etching. FIGS. 18-20, show example removing of dielectric material 38 from trenches 40U/40L and removing charge-passage material 34 above channel material 36 from trenches 40U. FIGS. 21-23 show using the construction of FIGS. 18-20 as a mask while etching through lowest portions of channel material 36, charge-passage material 34, charge-storage material 32, and charge-blocking material 30 to expose sacrificial material 77 of lowest first tier 22z through trenches 40U/40L. Etching may occur into material 77 as shown. Mask opening 81 in insulator material 80 (and/or in material 82 if present) may be widened in one or more of the example FIGS. 15-23 processing steps (not shown).

Referring to FIGS. 24-26, exposed sacrificial material 77 (not shown) has been isotropically etched (e.g., using H₃PO₄where such comprises silicon nitride and using tetramethylammonium hydroxide where such comprises polysilicon) from lowest first tier 22z through trenches 40U/40L. In one example and as shown, channel material 36 that was in trenches 40U/40L (not shown) has also been etched, for example when materials 36 and 77 are of the same etchable composition (e.g., suitably doped polysilicon).

Referring to FIGS. 27 and 28, charge-passage material 34 in trenches 40U/40L (not shown) has been removed, for example by isotropic etching. Such is also shown as having reduced the thickness of material 24 of tiers 20Lx and 20Lz. Such is also shown as removing charge-blocking material 30 in tier 22Lz of channel-material-string structure 53 (for example when material 30 comprises silicon dioxide). FIGS. 29 and 30 show subsequent removal of charge-storage material 32 from trenches 40U/40L (not shown) and from channel-material-string structure 53 in tier 22Lz. FIGS. 31-33 show subsequent removal of charge-blocking material 30 from trenches 40U/40L (not shown), charge-passage material 34 from channel-material-string structure 53 in tier 22Lz, and remaining material 24 (not shown) from tiers 20Lx and 20Lz. A sidewall 41 of channel material 36 of channel-material-string structure 53 in tier 22Lz has been exposed thereby.

By way of examples only, one or more of the removed materials 36, 34, 32, and 30 may comprise silicon dioxide, silicon nitride, or multiple layers that individually comprising one of silicon dioxide or silicon nitride. Modified or different chemistries may be used for sequentially etching silicon dioxide and silicon nitride selectively relative to the other. As examples, a solution of 100:1 (by volume) water to HF will etch silicon dioxide selectively relative to silicon nitride, whereas a solution of 1000:1 (by volume) water to HF will etch silicon nitride selectively relative to silicon dioxide. The artisan is capable of selecting other chemistries for etching other different materials.

Referring to FIGS. 34-36, conductive material 42 has been formed in lowest first tier 22Lz and that directly electrically couples together channel material 36 of individual channel-material-string structure 53 and conductor material 17 of conductor tier 16, followed by removal of conductive material 42 from trenches 40U/40L.

Referring to FIGS. 37-42, material 26 (not shown) of conductive tiers 22U/22L has been removed, for example by being isotropically etched away through trenches 40U/40L ideally selectively relative to the other exposed 7506P.doc 13 materials (e.g., using liquid or vapor H₃PO₄as a primary etchant where material 26 is silicon nitride and other materials comprise one or more oxides or polysilicon). Material 26 (not shown) in conductive tiers 22U/22L in the example embodiment is sacrificial and has been replaced with conducting material 48, and which has thereafter been removed from trenches 40U/40L, thus forming individual conductive lines 29 (e.g., wordlines) and elevationally-extending strings 49 of individual transistors and/or memory cells 56.

A thin insulative liner (e.g., Al₂O₃and not shown) may be formed before forming conducting material 48. Approximate locations of transistors and/or memory cells 56 are indicated with a bracket in FIG. 40 and some with dashed outlines in FIGS. 37-39, with transistors and/or memory cells 56 being essentially ring-like or annular in the depicted example. Alternately, transistors and/or memory cells 56 may not be completely encircling relative to individual channel openings 39/25 such that each channel opening 39/25 may have two or more elevationally-extending strings 49 (e.g., multiple transistors and/or memory cells about individual channel openings in individual conductive tiers with perhaps multiple wordlines per channel opening in individual conductive tiers, and not shown). Conducting material 48 may be considered as having terminal ends 50 (FIG. 40) corresponding to control-gate regions 52 of individual transistors and/or memory cells 56. Control-gate regions 52 in the depicted embodiment comprise individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be considered as a memory structure 65 that is laterally between control-gate region 52 and channel material 36. In one embodiment and as shown with respect to the example “gate-last” processing, conducting material 48 of conductive tiers 22U/22L is formed after forming channel openings 39/25 and/or trenches 40U/40L. Alternately, the conducting material of the conductive tiers may be formed before forming channel openings 39/25 and/or trenches 40U/40L (not shown), for example with respect to “gate-first” processing.

A charge-blocking region (e.g., charge-blocking material 30) is between storage material 32 and individual control-gate regions 52. A charge block may have the following functions in a memory cell: In a program mode, the charge block may prevent charge carriers from passing out of the storage material (e.g., floating-gate material, charge-trapping material, etc.) toward the control gate, and in an erase mode the charge block may prevent charge carriers from flowing into the storage material from the control gate. Accordingly, a charge block may function to block charge migration between the control-gate region and the storage material of individual memory cells. An example charge-blocking region as shown comprises insulator material 30. By way of further examples, a charge-blocking region may comprise a laterally (e.g., radially) outer portion of the storage material (e.g., material 32) where such storage material is insulative (e.g., in the absence of any different-composition material between an insulative storage material 32 and conducting material 48). Regardless, as an additional example, an interface of a storage material and conductive material of a control gate may be sufficient to function as a charge-blocking region in the absence of any separate-composition-insulator material 30. Further, an interface of conducting material 48 with material 30 (when present) in combination with insulator material 30 may together function as a charge-blocking region, and as alternately or additionally may a laterally-outer region of an insulative storage material (e.g., a silicon nitride material 32). An example material 30 is one or more of silicon hafnium oxide and silicon dioxide. Example channel materials 36 include appropriately-doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN).

Intervening material 57 has been formed in trenches 40U/40L and thereby laterally-between and longitudinally-along immediately-laterally-adjacent memory-block regions 58. Intervening material 57 may provide lateral electrical isolation (insulation) between immediately-laterally-adjacent memory blocks. Such may include one or more of insulative, semiconductive, and conducting materials and, regardless, may facilitate conductive tiers 22U/22L from shorting relative one another in a finished circuitry construction. Example insulative materials are one or more of SiO₂, Si₃N₄, Al₂O₃, and undoped polysilicon. Intervening material 57 may include through array vias (not shown).

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

Alternate embodiment constructions may result from method embodiments described above, or otherwise. Regardless, embodiments of the invention encompass memory arrays independent of method of manufacture. Nevertheless, such memory arrays may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may incorporate, form, and/or have any of the attributes described with respect to device embodiments.

In one embodiment, a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) comprises laterally-spaced memory blocks (e.g., 58) individually comprising a vertical stack (e.g., 18U/18L) comprising alternating insulative tiers (e.g., 20U/20L) and conductive tiers (e.g., 22U/22L). Channel-material-string structures (e.g., 53) of memory cells (e.g., 56) extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion (e.g., 95, FIG. 42) above and joined with a lower portion (e.g., 96, FIG. 42). The upper portion comprises an average longitudinal axis (e.g., 85) and the lower portion comprising an average longitudinal axis (e.g., 75). The upper-portion average longitudinal axis is laterally offset relative to the lower-portion average longitudinal axis in a vertical cross-section (e.g., that of FIGS. 38 and 42) where the upper and lower portions join. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56) comprises laterally-spaced memory blocks (e.g., 58) individually comprising a vertical stack (e.g., 18U/18L) comprising alternating insulative tiers (e.g., 20U/20L) and conductive tiers (e.g., 22U/22L). Channel-material-string structures (e.g., 53) of memory cells (e.g., 56) extend through the insulative tiers and the conductive tiers. A wall (e.g., made of intervening material 57) is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The wall comprises two external jog surfaces (e.g., 90 and 92 in FIG. 41) above an uppermost of the conductive tiers (e.g., uppermost 22U when comprising upper stack 18U) in a vertical cross-section (e.g., that of FIGS. 38 and 41). In this document, a “jog surface” is characterized or defined by an abrupt change in direction [at least 15° ] in comparison to external surfaces of a channel-material-string structure that are immediately-above and immediately-below the jog surface. The wall is laterally narrower immediately-directly-above the two external jog surfaces than immediately-directly-below the two external jog surfaces. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within two stacks or two decks of such components above or as part of an underlying base substrate (albeit, the two stacks/decks may each have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks and different stacks/decks may be of the same thickness or of different thicknesses relative one another. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time. Alternately, aspects of the processing(s) or construction(s) may be with respect to a single stack or single deck above or part of an underlying base substrate.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

In this document unless otherwise indicated, “elevational”, “higher”, “upper”, “lower”, “top”, “atop”, “bottom”, “above”, “below”, “under”, “beneath”, “up”, and “down” are generally with reference to the vertical direction. “Horizontal” refers to a general direction (i.e., within 10 degrees) along a primary substrate surface and may be relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Reference to “exactly horizontal” is the direction along the primary substrate surface (i.e., no degrees there-from) and may be relative to which the substrate is processed during fabrication. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space. Additionally, “elevationally-extending” and “extend(ing) elevationally” refer to a direction that is angled away by at least 45° from exactly horizontal. Further, “extend(ing) elevationally”, “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like with respect to a field effect transistor are with reference to orientation of the transistor's channel length along which current flows in operation between the source/drain regions. For bipolar junction transistors, “extend(ing) elevationally” “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like, are with reference to orientation of the base length along which current flows in operation between the emitter and collector. In some embodiments, any component, feature, and/or region that extends elevationally extends vertically or within 100 of vertical.