410 in contact with the first support 600 may be made of silicon, and when the first support 600 is made of dummy silicon (e.g., silicon), the first support 600 may have the same physical properties as or similar physical properties to the second base chip 410. The dummy silicon may be silicon, and a pattern formed of dummy silicon may be a pattern without other material patterns (e.g., metal/conductor patterns) included inside of the silicon pattern. Accordingly, since the coefficients of thermal expansion of the first support 600 and the second base chip 410 are the same or similar, coefficients of thermal expansion (CTE) of the first support 600 and the second base chip 410 may be the same and may not mismatch.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “lower” versus “directly lower,” “upper” versus “directly upper,” etc.).

According to embodiments, the first support 600 may be formed of or may be a semiconductor chip. The semiconductor chip may be a controller chip, a frequency boosting interface (FBI) chip, or a dynamic random access memory (D-RAM) chip. A detailed description about the semiconductor chip support 600 will be described later with reference to FIGS. 4 to 6.

FIG. 1C is a cross-sectional view for explaining the position of the first support 600 of the semiconductor package 10 of FIG. 1A.

Referring to FIG. 1C, the semiconductor package 10 may include a package substrate 100, first and second chip stacked structures 300 and 400, and a first support 600. The first chip stacked structure 300 may include a first base chip 310 and first stacked chips 330-1 and 330-2, and the second chip stacked structure 400 may include a second base chip 410 and second stacked chips 430-1 and 430-2.

The first support 600 is spaced apart from the first chip stacked structure 300 in the first direction, and supports the second chip stacked structure 400 by supporting an end portion of the lower surface of the second base chip 410 in the first direction.

The first imaginary line L1 may be a line extending in the Z-axis direction on a plane in which a side surface of the first base chip 310 positioned at an end of the first base chip 310 in the first direction is placed. For example, the first imaginary line L1 may be a line extending in a direction perpendicular to the upper surface of the package substrate 100 at the right (X-axis direction) end of the first base chip 310 or may be a straight line extending in a direction (Z-axis direction) parallel to the side surface of the first base chip 310 at the right (X-axis direction) end of the first base chip 310.

The second base chip 410 may be a stacked chip positioned at the lowermost level/position/end among the stacked chips of which center is positioned on the side in the first direction (e.g., at the right-hand side) from the first imaginary line L1. For example, the second base chip 410 may be a chip located at the lowermost position/end while the center of the chip is located to the right of the first imaginary line L1 among the chips stacked on the package substrate 100.

The second base chip 410 may be a criterion for distinguishing the first chip stacked structure 300 from the second chip stacked structure 400. Based on the second base chip 410, the first chip stacked structure 300 may include or be formed of chips stacked/positioned under the second base chip 410, and the second chip stacked structure 400 may include or be formed of the second base chip 410 and chips stacked on/above the second base chip 410.

The position of the second base chip 410 will be described in more detail below.

The chips stacked on the package substrate 100 may include or may be chips offset-stacked in a cascade type, e.g., a step type, in the first direction. In the offset stacking chips, the centers of the chips may be positioned in/along the first direction, e.g., in a plan view. A center of each chip may be positioned farther on the right (e.g., in the first direction) than a center of a chip positioned immediately below the chip due to the cascade type stacking. Conversely, the center of each chip may be located in/along the second direction. A center of each chip may be positioned farther on the left (e.g., in the second direction) than a center of an offset-stacked chip positioned immediately above the chip.

In the semiconductor package 10 of the inventive concept, among the chips stacked in the cascade type on the package substrate 100, a chip located at the lowermost end among the chips whose centers are located on/at the right-hand side with respect to or from the first imaginary line L1 may be specified as the second base chip 410. When the second base chip 410 is specified, among the chips stacked on the package substrate 100, chips offset-stacked along the first direction on/above the upper surface of the second base chip 410 may be specified as second stacked chips 430-1 and 430-2, and a set of the second base chip 410 and the second stacked chips 430-1 and 430-2 may be a second chip stacked structure 400. For example, each chip of the second chip stacked structure 400 may have a center which does not vertically overlap the first base chip 310.

In addition, as the second base chip 410 is specified, the chip located just below the second base chip 410 may be the first stacked chip 330-2 located at the uppermost level/position/end of the first chip stacked structure 300, and a set of stacked chips from the first base chip 310 to the first stacked chip 330-2 may be the first chip stacked structure 300.

As a result, the first support 600 may support the second chip stacked structure 400 by supporting the second base chip 410, e.g., the chip located at the lowermost level/position/end among the chips whose centers are located farther on the right than the right end of the first base chip 310.

FIG. 2 is a cross-sectional view for explaining an effect of a semiconductor package according to an embodiment.

Referring to FIG. 2, the semiconductor package 10 may include a first chip stacked structure 300, a second chip stacked structure 400, and a first support 600. By cascade-type stacking of the first and second chip stacked structures 300 and 400 in the first direction, as the second base chip 410 and the second stacked chips 430-1 and 430-2 constituting the second chip stacked structure 400 are stacked, centers of the chips may be gradually positioned to the right (e.g., gradually shifting to the right). Accordingly, each of the second base chip 410 and the second stacked chips 430-1 and 430-2 may have a center of the chip located on/at the right-hand side with respect to or from the end of the first base chip 310 in the first direction (e.g., the right-hand side end).

The load (e.g., gravity) of the chip may act or may be applied downwardly in a direction from the center of the chip toward the upper surface of the package substrate 100. For example, gravity or gravitational forces of the chips may be applied downwardly, e.g., from centers of the chips toward the package substrate 100. Therefore, the load/gravity of the second base chip 410 acts or is applied downwardly as indicated by an arrow at the center 411 of the second base chip, and the loads (e.g., gravity or gravitational forces) of the second stacked chips 430-1 and 430-2 act or are applied in a downward direction as indicated by arrows at the centers 431-1 and 431-2 of the second stacked chips.

Since the centers of the second base chip 410 and the second stacked chips 430-1 and 430-2 are all located on/at the right-hand side with respect to or from the right end of the first base chip 310, loads/gravity of the second base chip 410 and the second stacked chips 430-1 and 430-2 may also act on or be applied to the right-hand side from the right end of the first base chip 310. Accordingly, a phenomenon in which the load is concentrated on the right end of the first base chip 310 may occur without the first support 600. In addition, a clockwise moment may be applied to the right end of the first base chip 310 by the loads in case the first support is not formed thereby not supporting the stacked chips.

As a result, due to the cascade-type stacking structure of which chips are gradually shifting in the first direction from the first base chip 310 to the uppermost second stacked chip 430-2, a load and moment concentration may occur at the right end of the first base chip 310 in case the first support 600 does not support the stacked chips. However, while the first support 600 supports the second chip stacked structure 400, a vertical drag force (e.g., reaction force) is generated on the upper surface of the first support 600, and since the vertical drag/reaction force is applied in a direction opposite to the load of the second base chip 410 and the second stacked chips 430-1 and 430-2, the load (gravity or gravitational force) applied to the right end of the first base chip 310 may be dispersed/distributed/dissipated. In addition, since a counterclockwise moment is applied to the right end of the first base chip 310 by the vertical drag/reaction force, the clockwise moment applied to the right end of the first base chip 310 may be offset/dissipated.

In the case of a general semiconductor package, since the position of the support is not properly limited, the load of the chip stacked structure 200 was not efficiently distributed/dispersed/dissipated, and since the moment applied to the right end of the first base chip 310 is also not effectively offset, the semiconductor package was frequently defective.

However, in the semiconductor package 10 of the inventive concept, the first support 600 may support the lower end of the second base chip 410. The second base chip 410 may be a chip located at the lowermost end of the stacked chips that apply a clockwise moment to the right end of the first base chip 310 by the cascade stacking type. Therefore, when the first support 600 supports the lower end of the second base chip 410, since the first support 600 supports all the chips applying a clockwise moment to the right end of the first base chip 310, while distributing/dispersing the load (gravity or gravitational force) generated by the second base chip 410 and the second stacked chips 430-1 and 430-2 and applied downwardly toward the first support 600, the clockwise moment applied to the right end of the first base chip 310 may be offset/dissipated most efficiently.

As a result, in terms of load/gravity distribution/dispersion of the chip stacked structure 200, in the semiconductor package 10 according to embodiments of the inventive concept, as the first support 600 supports the lower end of the second base chip 410, the embodiment is beneficial to prevent a crack from occurring at the right end of the first base chip 310. For example, crack defects of the first base chip 310 will be improved.

In addition, a die attaching process may be performed on the semiconductor package. The die attaching process may press the upper surface of the chip stacked structure 200 with a die attaching apparatus 1000. Accordingly, an external force acts on (e.g., is applied to) the upper surface of the chip stacked structure 200 as indicated by an arrow in FIG. 2 and the external force is applied in the same direction as the load (gravity or gravitational force) of the chip stacked structure 200, so that the load and moment may be concentrated on the right end of the first base chip 310 by the same mechanism as the load/gravity of the second base chip 410 and the second stacked chips 430-1 and 430-2 is concentrated at the right end of the first base chip 310.

However, in the semiconductor package 10 according to the embodiments of the inventive concept, as the first support 600 supports the lower end of the second base chip 410, similarly to effectively offsetting the load and moment applied to the right end of the first base chip 310, even during the die attaching process, the first support 600 may effectively offset the load and moment applied to the right end of the first base chip 310 by the same mechanism.

After all, even during the die attaching process, in the semiconductor package 10 according to embodiments of the inventive concept, as the first support 600 supports the lower end of the second base chip 410, the embodiments may prevent a crack from occurring at the right end of the first base chip 310.

In addition, as the load and moment applied to the right end of the first base chip 310 is effectively offset/dissipated, in terms of action-reaction, a load and a moment applied to the vicinity of the first stacked chip 330-1 in contact with the first base chip 310 may also be effectively offset/dissipated.

As the semiconductor package 10 of the inventive concept appropriately limits the position of the first support 600, the semiconductor package 10 may to efficiently prevent cracking of chips stacked on the package substrate 100 and provide a reliable semiconductor package.

FIG. 3A is a cross-sectional view of a semiconductor package 11 according to an embodiment, and FIG. 3B is a plan view of the semiconductor package of FIG. 3A. Hereinafter, overlapping contents of the semiconductor package 10 of FIG. 1A and the semiconductor package 11 of FIG. 3A will be omitted, and differences will be mainly described.

Referring to FIGS. 3A and 3B, the semiconductor package 11 may include a package substrate 100, an external connection bump 110, a substrate pad 130, a chip stacked structure 200, a bonding pad 230, a bonding wire 240, and a first support 610 and the chip stacked structure 200 may include a first chip stacked structure 300 and a second chip stacked structure 400.

Right-hand side end of the first support 610 may be on the second direction side (at the left-hand side) from a right-hand side end of the second stacked chip 430-2 when the first support 610 is at the right-hand side from the first base chip 310. For example, the right end of the second stacked chip 430-2 positioned at the uppermost level/end of the second chip stacked structure 400 may be on the right-hand side from the right end of the first support 610.

Accordingly, the first support 610 may not be seen from above as the first support 610 is completely covered by the second chip stacked structure 400. For example, the second chip stacked structure 400 may completely overlap the first support 610 in a vertical direction.

When the first direction end (right end) of the first support 610 is located on the left-hand side from the first direction end (right end) of the second stacked chip 430-2 positioned at the uppermost level/end of the second chip stacked structure, e.g., when the first support 610 is completely covered by the second chip stacked structure 400, the internal space of the semiconductor package 11 may be reduced, and a compact semiconductor package may be provided.

FIG. 4 is a cross-sectional view illustrating a semiconductor package 12 according to an embodiment. Hereinafter, overlapping contents of the semiconductor package 10 of FIG. 1A and the semiconductor package 12 of FIG. 4 will be omitted, and differences will be mainly described.

Referring to FIG. 4, the semiconductor package 12 may include a package substrate 100, an external connection bump 110, a substrate pad 130, a chip stacked structure 200, a bonding pad 230, a bonding wire 240, a first support 620, and a connection bump 621, and the chip stacked structure 200 may include a first chip stacked structure 300 and a second chip stacked structure 400.

According to embodiments, the first support 620 is a semiconductor chip, and may be a controller chip, an FBI chip, or a D-RAM chip.

According to embodiments, the semiconductor package 12 uses a controller chip serving as a controller for the chips in the first and second chip stacked structures 300 and 400 as a first support 620, such that the size of the semiconductor package may be reduced.

According to embodiments, the semiconductor package 12 uses the FBI chip serving as an interface to change an input frequency and transmit the changed input frequency to each semiconductor chip as the first support 620, such that the size of the semiconductor package may be reduced.

According to embodiments, the semiconductor package 12 uses a D-RAM chip, which is a heterogeneous semiconductor device mounted together with the chip stacked structure 200, as the first support 620, such that the size of the semiconductor package may be reduced.

In this case, the first support 620 may be electrically connected to the package substrate 100 through the connection bump 621. The first support 620 may be electrically connected to the first and second chip stacked structures 300 and 400 through the package substrate 100 and bonding wires 240.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, may be used herein for ease of description to describe positional relationships. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures.

FIG. 5 is a cross-sectional view illustrating a semiconductor package 13 according to an embodiment. Hereinafter, overlapping contents of the semiconductor package 12 of FIG. 4 and the semiconductor package 13 of FIG. 5 will be omitted, and differences will be mainly described.

Referring to FIG. 5, the semiconductor package 13 includes a package substrate 100, an external connection bump 110, a substrate pad 130, a chip stacked structure 200, a bonding pad 230, a bonding wire 240, a first support 630, a substrate pad 631, a bonding wire 632, and a bonding pad 633, and the chip stacked structure 200 may include a first chip stacked structure 300 and a second chip stacked structure 400.

According to embodiments, the first support 630 is a semiconductor chip, and may be a controller chip, an FBI chip, or a D-RAM chip.

In this case, the first support 630 may be electrically connected to the package substrate 100 through the bonding pad 633, the bonding wire 632, and the substrate pad 631.

FIG. 6 is a cross-sectional view illustrating a semiconductor package 14 according to an embodiment. Hereinafter, overlapping contents of the semiconductor package 13 of FIG. 5 and the semiconductor package 14 of FIG. 6 will be omitted, and differences will be mainly described.

Referring to FIG. 6, the semiconductor package 14 may include a package substrate 100, an external connection bump 110, a substrate pad 130, a chip stacked structure 200, a bonding pad 230, a bonding wire 240, a first support 640, a substrate pad 643, a bonding wire 644, and a bonding pad 645. The chip stacked structure 200 may include a first chip stacked structure 300 and a second chip stacked structure 400.

According to embodiments, the first support 640 may include a first semiconductor chip 641 and a second semiconductor chip 642. The second semiconductor chip 642 may be positioned on an upper surface of the first semiconductor chip 641.

According to embodiments, the first semiconductor chip 641 may be a controller chip, an FBI chip, or a D-RAM chip. The second semiconductor chip 642 may be a controller chip, an FBI chip, or a D-RAM chip.

In the semiconductor package 14 of the present embodiment, the first support 640 includes two semiconductor chips, but the number of semiconductor chips of the first support 640 is not limited to two. For example, the first support 640 may include three or more chips.

According to embodiments, a plurality of substrate pads 643, bonding wires 644, and bonding pads 645 may be provided respectively corresponding to the number of semiconductor chips of the first support 640.

In this case, the first semiconductor chip 641 may be electrically connected to the package substrate 100 through the bonding pad 645, the bonding wire 644, and the substrate pad 643, and the second semiconductor chip 642 may be electrically connected to the package substrate 100 through a bonding pad 645, a bonding wire 644, and a substrate pad 643 corresponding to the second semiconductor chip 642. The first and second semiconductor chips 641 and 642 may be electrically connected to the first and second chip stacked structures 300 and 400 through the package substrate 100 and bonding wires 240.

According to embodiments, the semiconductor package 14 uses the first semiconductor chip 641 and the second semiconductor chip 642 stacked/disposed on the first semiconductor chip 641 as a first support 640 such that the embodiments are beneficial to reduce the size of the semiconductor package.

FIG. 7 is a plan view illustrating a semiconductor package 15 according to an embodiment. Hereinafter, overlapping contents of the semiconductor package 10 of FIG. 1A and the semiconductor package 15 of FIG. 7 will be omitted, and differences will be mainly described.

Referring to FIG. 7, the semiconductor package 15 may include a package substrate 100, an external connection bump 110, a substrate pad 130, a first chip stacked structure 300, a second chip stacked structure 400, a bonding pad 230, a bonding wire 240, and a plurality of first supports 600-1 and 600-2.

While being spaced apart from each other in the third direction and positioned on the upper surface of the package substrate 100, the plurality of first supports 600-1 and 600-2 may support the lower surface of the second base chip 410 to support the second chip stacked structure 400.

According to embodiments, the plurality of first supports 600-1 and 600-2 are semiconductor chips, and each of which may be a controller chip, an FBI chip, or a D-RAM chip, and the plurality of first supports 600-1 and 600-2 may be different types of semiconductor chips from each other.

According to embodiments, the semiconductor package 15 supports the second chip stacked structure 400 with a plurality of first supports 600-1 and 600-2 composed of semiconductor chips, such that it is possible to reduce the size of the semiconductor package while properly disposing/arranging the semiconductor chips. While two first supports 600-1 and 600-2 are illustrated in FIG. 7, the embodiments are not limited thereto, and three or more first supports may be provided in certain embodiments.

FIG. 8A is a cross-sectional view for explaining a semiconductor package 20 according to an embodiment, and FIG. 8B is a cross-sectional view for explaining the positions of the first support 600 and the second support 700 of the semiconductor package 20 of FIG. 8A. Hereinafter, overlapping contents of the semiconductor package 10 of FIG. 1A and the semiconductor package of FIG. 8A will be omitted, and differences will be mainly described.

Referring to FIGS. 8A and 8B, the semiconductor package 20 may include a package substrate 100, an external connection bump 110, a substrate pad 130, a chip stacked structure 201, a bonding pad 230, a bonding wire 240, a first support 600, and a second support 700. The chip stacked structure 201 may include a first chip stacked structure 300, a second chip stacked structure 400, and a third chip stacked structure 500.

According to some embodiments, the first support 600 and the second support 700 may be formed of dummy silicon, e.g., a silicon pattern.

According to certain embodiments, the first support 600 and the second support 700 are semiconductor chips, and each of which may be a controller chip, an FBI chip, or a D-RAM chip, and the first support 600 and the second support 700 may be different types of semiconductor chips from each other. In certain embodiments, the plurality of first supports 600-1 and 600-2 of FIG. 7 may replace the first support 600 of FIGS. 8A and 8B, and the plurality of first supports 600-1 and 600-2 may be different types of semiconductor chips from each other.

In embodiments, the second support 700 may be positioned to be spaced apart from the first and second chip stacked structures 300 and 400 in the first direction on the upper surface of the first support 600. The second support 700 may support/contact a lower surface of the third base chip 510 to support the third chip stacked structure 500. In embodiments, the second support 700 may support the third chip stacked structure 500 by supporting/contacting an end portion of the lower surface of the third base chip 510 in the first direction.

The second imaginary line L2 may be a line extending in a vertical direction and disposed in a plane in which a side surface of the second base chip 410 in the first direction disposed. For example, the second imaginary line L2 may be a line extending perpendicularly to the upper surface of the package substrate 100 at the right (X-axis direction) end of the second base chip 410 in a cross-sectional view in which the first base chip 310 is positioned at the left-hand side from the first support 600 as shown in FIGS. 8A and 8B.

The third base chip 510 may be a stacked chip located at the lowermost level/end among stacked chips whose centers are positioned on the first direction side (right-hand side) with respect to or from the second imaginary line L2. For example, the third base chip 510 may be a chip located at the lowermost level/end while the center of the chip is located at the right-hand side from the second imaginary line L2 among the chips stacked on the package substrate 100, e.g., in a cross-sectional view in which the first base chip 310 is positioned at the left-hand side from the first support 600 as shown in FIGS. 8A and 8B.

The third base chip 510 may be a criterion for distinguishing the second chip stacked structure 400 from the third chip stacked structure 500. Based on the third base chip 510, the second chip stacked structure 400 may include chips stacked/placed on the first chip stacked structure 300 while being stacked/placed under the third base chip 510, and the third chip stacked structure 500 may include or be formed of a third base chip 510 and chips stacked on the third base chip 510.

The position of the third base chip 510 will be described in more detail below.

The chips stacked on the package substrate 100 may include chips offset-stacked in a cascade type, e.g., a step type, in the first direction. In the offset stacking chips, the center of a chip may be positioned in the first direction, e.g., on the right-hand side, from the center of a chip immediately below the chip due to the cascade type stacking. For example, the center of the chip at a lower level/end may be located in the second direction, e.g., on the left-hand side from a center of the chip that is offset-stacked directly at the upper level/end.

In the semiconductor package 20 of the inventive concept, among the chips stacked in the cascade type on the package substrate 100, a chip located at the lowermost level/end of the chips whose center is located on the right-hand side with respect to or from the second imaginary line L2 may be specified/classified as the third base chip 510. When the third base chip 510 is specified, among the chips stacked on the package substrate 100, chips offset-stacked along the first direction on the upper surface of the third base chip 510 may be specified/classified as third stacked chips 530-1 and 530-2, and a set of the third base chip 510 and the third stacked chips 530-1 and 530-2 may be a third chip stacked structure 500. For example, each chip of the third chip stacked structure 500 may have a center which does not vertically overlap the second base chip 410. The center of each chip in the third chip stacked structure 500 also does not vertically overlap the first base chip 310.

In addition, as the third base chip 510 is specified, the chip located just below the third base chip 510 may be the second stacked chip 430-2 located at the uppermost end of the second chip stacked structure 400, and referring to FIG. 1C, a set of stacked chips from the second base chip 410 to the second stacked chip 430-2 may become the second chip stacked structure 400. The first base chip 310, the first stacked chips 330-1 and 330-2 and the first chip stacked structure 300 may be substantially the same as or similar to those specified in FIGS. 1A to 1C, and detailed descriptions thereof will be omitted.

As a result, the second support 700 may support the third chip stacked structure 500 by supporting/contacting the third base chip 510, e.g., the chip located at the lowermost end among the chips whose centers are located on/at the right-hand side from the right end of the second base chip 510.

Even if the chip stacked structure 201 stacked in the cascade type is elongated in the first direction, as the semiconductor package 20 of the inventive concept is provided with a first support 600 and a second support 700, it is possible to efficiently distribute/disperse/dissipate the load of the chip stacked structure 201 and effectively offset/dissipate the moment applied to the stacked chips.

For example, as the semiconductor package 20 of the inventive concept appropriately limits the positions of the first support 600 and the second support 700, the embodiments of FIGS. 8A and 8B may to efficiently prevent cracking of chips stacked on the package substrate 100 and provide a reliable semiconductor package.

FIG. 9 is a cross-sectional view illustrating a semiconductor package 21 according to an embodiment. Hereinafter, overlapping contents of the semiconductor package 10 of FIG. 1A and the semiconductor package 21 of FIG. 9 will be omitted, and differences will be mainly described.

Referring to FIG. 9, the semiconductor package 21 may include a package substrate 100, an external connection bump 110, a substrate pad 130, a chip stacked structure 201, a bonding pad 230, a bonding wire 240, a first support 650, and a second support 750. The chip stacked structure 201 may include a first chip stacked structure 300, a second chip stacked structure 400, and a third chip stacked structure 500.

In embodiments, the second support 750 is spaced apart from the first support 650 in the first direction, e.g., to the right, and is located on the upper surface of the package substrate 100, and may be spaced apart from the first and second chip stacked structures 300 and 400 in the first direction. The second support 750 may support the lower surface of the third base chip 510 to support the third chip stacked structure 500. In embodiments, the second support 700 may support the third chip stacked structure 500 by supporting an end portion of a lower surface of the third base chip 510 in the first direction.

FIG. 10A is a cross-sectional view for explaining a semiconductor package 30 according to an embodiment, and FIG. 10B is a cross-sectional view for explaining the position of the first support 600 of the semiconductor package 30 of FIG. 10A. Hereinafter, overlapping contents of the semiconductor package 10 of FIG. 1A and the semiconductor package 30 of FIG. 10A will be omitted, and differences will be mainly described.

Referring to FIGS. 10A and 10B, the semiconductor package 30 may include a package substrate 100, an external connection bump 110, a substrate pad 130, a plurality of chip stacked structures 200 and 202, a bonding pad 230, a bonding wire 240, and a first support 600. The chip stacked structure 200 located on the left may include a first chip stacked structure 300 and a second chip stacked structure 400, and the chip stacked structure 202 located on the right may include a fourth chip stacked structure 800 and a fifth chip stacked structure 900.

The left chip stacked structure 200 may be substantially the same as or similar to that described with reference to