126 of the first additional cell, such that the first rules are re-applied to only the initial cells that surround the final location 126.

If there are multiple locations that satisfy the additional rules, then the first rules of the cells at locations 102 can be considered for determining an optimal location of the first additional cell. A threshold of a probability of design rule success can be set. For example, a threshold of 100% probability can be set. In this example with respect to the third circuit design layout 120 of FIG. 1, four of the five candidate locations 106 can be removed as candidate locations in order for the probability of design rule success to reach 100%, which satisfies the 100% threshold. If the threshold is 80%, then three out of the five locations 106 can be removed. Then with the 80% threshold satisfied with the remaining two candidate locations 106, further optimizations can be performed prior to finalizing the placement and routing of the circuit design layout.

FIG. 2 provides an operation flow diagram 200 for calculating probability of success for cell placement and updating (maintaining) a library data structure for future placement of cells according to some embodiments of the present disclosure. The embodiments described herein with reference to FIG. 2 relate to dynamically updating the values of the probability of design rule success for cells by continuously data-mining actual optimizations and storing the continuously updated values in a library data structure along with contextual changes happening in the layout. This can be done after an initial placement of cells is determined and subsequent optimizations of the circuit design layout are being performed.

Referring to FIG. 2, the diagram 200 illustrates an operation 202 of initializing the circuit design layout of cells. This can include the initial placement of cells at locations (e.g., locations 102 of FIG. 1). This initial placement can include making sure that the cells will honor their respective rules. Next, at operation 204, one or more additional cells can be added. At operation 206, additional information (e.g., design rules) regarding the one or more additional cells can be considered to calculate the probability of design rule success for placement of the added one or more additional cells at various locations (operation 207). At operation 208, the one or more additional cells can be placed at various candidate locations. At operation 210, additional feedback (e.g., additional rules or performance information) regarding the one or more additional cells can provided back to operation 207 for further determining the probability of design rule success.

Operation 212 is responsive to a cell being placed at a particular location (which can be based on a calculated probability of design rule success) and can include providing the determined probabilities of design rule success to a computer system that includes maintained libraries (e.g., databases). At operation 216, a library data structure (e.g., a table) containing a probability of design rule success of each cell at each location can be dynamically updated based on the received determined probabilities of success, optimization result (from 220), other factors such as an available area constraint, a floorplan constraint, and a neighboring constraint. Furthermore, the dynamically updated library data structure can be provided at operation 218 so that optimization operations 214 can be performed to further optimize the circuit design layout. Optimization operations 214 can include techniques to improve timing, power and/or area by adding new cells or sizing pre-existing cells along a timing path (in contrast to placement techniques that involve placing newly added or sized cells on the layout such that they honor all of the design and technology node rules). Timing, power and area can be determined by static timing analysis. For example, the system can determine a setup/hold timing violation by performing a static timing analysis and then the optimization operations 214 can insert an additional repeater circuit component (e.g., a buffer or an inverter) in the path where the timing violation occurred. Further, optimization operations 214 can also replace a cell with a different cell that has a higher or lower drive strength in order to improve the setup/hold time and avoid a timing violation. Results of the optimization operations 214 can be provided, at operation 220, back to the system that dynamically updates the library data structure. For example, during the optimization operations 214, additional cells might be added or resizing of existing cells to improve timing, power and/or area can be performed. These optimizations operations 214 can have a feedback loop (operations 216, 218 and 220) that considers the constantly updated library data structures. The library data structures can be updated by additional circuit design layouts. This way, various circuit design layouts can be optimized and improved based on the success of other circuit design layouts. As operations 206-220 are performed, additional information can be gathered and implemented as a machine learning model. For example, location information and constraints 224, available area information and constraints 226, additional rules 228, neighboring cell information and constraints 230, and additional libraries 232 (e.g., that include probability of design rule success and/or library data structures) can be provided to a system and stored in storage 222. The system can then use the information from the storage 222 to obtain updated probabilities of success 234. Specifically, the information from the storage 222 can be used to predict a probability of design rule success for current circuit design layout placement and optimization operations based on historical information and can develop a machine learning model (e.g., a library learning model) that can use current cell libraries and rules to improve placement and optimization operations. These dynamically updated libraries of FIG. 2 can be implemented to carry out the operations described above with reference to FIG. 1.

FIG. 3 shows an example of considering whether to place cell A or cell B at a particular location according to some embodiments of the present disclosure.

Embodiments related to FIG. 3 implement the placement operations described with respect to FIGS. 1 and 2 and consider the determined probabilities of design rule success as an additional benefit when choosing between two different cells for placement in a location when performing optimizations for timing, power, and area improvement. FIG. 3 illustrates a first circuit design layout 300 and a second circuit design layout 310. In this example, cell A and cell B are competing for a location in the circuit design layout.

In the first circuit design layout 300, an optimization technique 302 picks cell A to be located at location L1 (as opposed to cell B), because cell A has a better optimization metric (e.g., better timing, power and/or area). However, in the second circuit design layout 310, the placement and optimization techniques 304 described herein select cell B to be located at location L1 (as opposed to cell A), because cell A only has a 10% probability of design success at location L1 and cell B has an 80% probability of design success at location L1. Therefore, even though cell B has an inferior optimization metric as compared to cell A, cell B is selected at the better solution because of the higher probability of design rule success. These techniques can be implemented by (i) determining an optimization metric (e.g., benefit) and a probability of design rule success of locating the first additional cell (e.g., cell B) in a given location of the candidate locations, (ii) determining an optimization metric (e.g., benefit) and a probability of design rule success of locating a second additional cell (e.g., cell A) in the given location, wherein the optimization metric (e.g., benefit) of locating the second additional cell at the given location is greater than the optimization metric (e.g., benefit) of locating the first additional cell at the given location and wherein the probability of design rule success of locating the second additional cell in the given location is less than the probability of design rule success of locating the first additional cell in the given location, and (iii) selecting the first additional cell (e.g., cell B) to be located at the given location in dependence on the determined optimization metrics (e.g., benefits) and probabilities of design rule success (e.g., cell B is selected because it has higher overall benefit in terms of QOR optimization and probability of design rule success in comparison to cell A).

FIG. 4 provides an operation flow diagram of implementing dynamic optimization according to some embodiments of the present disclosure. Specifically, FIG. 4 illustrates an operation flow diagram 400 showing dynamic optimization of an entire circuit design layout of an integrated circuit. Operation 402 can perform placement and optimization for individual (new) cells in the circuit design layout and can perform placement and optimization for all cells in the circuit design layout. The results of the placement and optimization operation 402 can be used for the place and route flow operations 403 of the circuit design layout of the integrated circuit. Specifically, the results of the optimization operation 402 can be used for operations 404 including placement optimization, clock optimization and route optimization of the integrated circuit place and route flow 403.

FIG. 5 provides example improvements of runtimes required to perform placement operations in accordance with some embodiments of the present disclosure.

Specifically, FIG. 5 illustrates a table 500 that includes various designs 502 (i.e., Design A, Design B and Design C), baseline placement runtimes 504 while honoring all design rules for the various designs 502, new placement runtimes 506 for the various designs 502 using the placement and optimization techniques described herein, and runtime improvements 508 for the various designs 502. As illustrated, the runtime improvements using the placement and optimization techniques described herein can range from about 1.52 times faster to about 10 times faster.

FIG. 6 illustrates an example set of processes 600 used during the design, verification, and fabrication of an article of manufacture such as an integrated circuit to transform and verify design data and instructions that represent the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations.

The term ‘EDA’ signifies the term ‘Electronic Design Automation.’ These processes start with the creation of a product idea 610 with information supplied by a designer, information which is transformed to create an article of manufacture that uses a set of EDA processes 612. When the design is finalized, the design is taped-out 634, which is when artwork (e.g., geometric patterns) for the integrated circuit is sent to a fabrication facility to manufacture the mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is fabricated 636 and packaging and assembly processes 638 are performed to produce the finished integrated circuit 640.

Specifications for a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. A high-level of representation may be used to design circuits and systems, using a hardware description language (‘HDL’) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera. The HDL description can be transformed to a logic-level register transfer level (‘RTL’) description, a gate-level description, a layout-level description, or a mask-level description. Each lower representation level that is a less detailed description adds more useful detail into the design description, for example, more details for the modules that include the description. The lower levels of representation that are more detailed descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of representation language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each level of representation are enabled for use by the corresponding tools of that layer (e.g., a formal verification tool). A design process may use a sequence depicted in FIG. 6. The processes described by be enabled by EDA products (or tools).

During system design 614, functionality of an integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or lines of code), and reduction of time and energy, etc. Partitioning of the design into different types of modules or components can occur at this stage.

During logic design and functional verification 616, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, the components of the circuit may be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification may use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification.

During synthesis and design for test 618, HDL code is transformed to a netlist. In some embodiments, a netlist may be a graph structure where edges of the graph structure represent components of a circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to the specified design. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit may be tested to verify that the integrated circuit satisfies the requirements of the specification.