>1) may be in contact with the first source/drain pattern 150.

Each of the first gate structures GS1 will hereinafter be described as including three inner gate structures although it will be appreciated that other numbers of inner gate structures may be provided for a first gate structure GS1. It will also be appreciated that portions of the description below refer to the structure of a single element (e.g., a single first gate structure GS1) but such description should be understood as applicable to all such elements (e.g., applicable to plural first gate structures GS1).

Each of the first gate structures GS1 may include first, second, and third inner gate structures INT1_GS1, INT2_GS1, and INT3_GS1. The first, second, and third inner gate structures INT3_GS1, INT2_GS1, and INT1_GS1 may be sequentially disposed on the first lower pattern BP1.

The third inner gate structure INT3_GS1 may be disposed between the first lower pattern BP1 and a first sheet pattern NS1. The third inner gate structure INT3_GS1 may be disposed at a lowest location, among the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) of each of the first gate structures GS1. The third inner gate structure INT3_GS1 may be the lowermost inner gate structure.

Each of the first and second inner gate structures INT1_GS1 and INT2_GS1 may be disposed between two adjacent first sheet patterns NS1 in the third direction D3. The first inner gate structure INT1_GS1 may be disposed at a highest location, among the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) of each of the first gate structures GS1. The first inner gate structure INT1_GS1 may be the uppermost inner gate structure. The second inner gate structure INT2_GS1 may be disposed between the first and third inner gate structures INT1_GS1 and INT3_GS1.

The inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) may include a corresponding portion of the first gate electrode 120 and a first gate insulating film 130 surrounding the same. An inner gate structure (INT1_GS1, INT2_GS1, or INT3_GS1) is disposed between the corresponding adjacent first sheet patterns NS1 or between the first lower pattern BP1 and the first sheet patterns NS1.

In some examples, the width, in the first direction D1, of the first inner gate structure INT1_GS1 may be the same as the width, in the first direction D1, of the second inner gate structure INT1_GS2, and the width, in the first direction D1, of the third inner gate structure INT1_GS3 may be the same as the width, in the first direction D1, of the second inner gate structure INT1_GS2.

In other examples, the width, in the first direction D1, of the third inner gate structure INT1_GS3 may be greater than the width, in the first direction D1, of the second inner gate structure INT1_GS2, and the width, in the first direction D1, of the first inner gate structure INT1_GS1 may be the same as the width, in the first direction D1, of the second inner gate structure INT1_GS2.

The width of an inner gate structure (for example, the second inner gate structure INT1_GS2) may be measured midway between the two adjacent first sheet patterns NS1 that are opposite to each other in the third direction D3 (e.g., midway between an upper surface NS1_US and a bottom surface NS1_BS of two adjacent first sheet patterns NS1).

FIG. 4 illustrates a plan view at the level of the second inner gate structure INT2_GS1. Although not specifically illustrated, plan views at the levels of the first and third inner gate structures INT1_GS1 and INT1_GS3 may be similar to that illustrated in FIG. 4, except for parts where first source/drain contacts 180 are formed.

The first gate electrodes 120 may be formed on the first lower pattern BP1. With respect to a plan view, as shown in FIG. 1, the first gate electrodes 120 may intersect the first lower pattern BP1. Each first gate electrode 120 may surround first sheet patterns NS1 with respect to a cross sectional view.

Referring to a single first gate electrode 120, parts of the first gate electrode 120 may be disposed between every two adjacent first sheet patterns NS1 in the third direction D3. In a case where the first sheet patterns NS1 include lower and upper first sheet patterns NS1 that are adjacent to each other in the third direction D3, part of the first gate electrode 120 may be disposed between an upper surface NS1_US of the lower first sheet pattern NS1 and a bottom surface NS1_BS of the upper first sheet pattern NS1, and part of the first gate electrodes 120 may be disposed between the upper surface BS1_US of the lower first sheet pattern NS1 and a bottom surface of a lowermost first sheet pattern NS1.

The first gate electrodes 120 may be formed of and/or include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrodes 120 may include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), Al, copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and a combination thereof, but the present invention is not limited thereto. Here, the conductive metal oxide and the conductive metal oxynitride may include oxides of the aforementioned materials, but the present invention is not limited thereto.

A pair of first gate electrodes 120 may be disposed on both sides of a first source/drain pattern 150 that will be described later. The pair of first gate structures GS1 may be disposed on both sides, in the first direction D1, of the first source/drain pattern 150.

In some examples, a first gate electrode 120 adjacent to a first source/drain pattern 150 may be a normal gate electrode, which is used as the gate of a transistor to operate the transistor (e.g., to switch the transistor to an on (or conductive) or off (non-conductive) state). In some examples, first gate electrodes on both sides of a source/drain pattern 150 may be such normal gate electrodes of corresponding transistors. In another example, first gate electrode 120 on one side of the first source/drain pattern 150 may be a normal gate electrode and used as a gate of a transistor, and a first gate electrode 120 on the other side of the first source/drain pattern 150 may be a dummy gate electrode.

A lowermost one of the first gate insulating films 130 may extend along the upper surface of the field insulating film 105 and the upper surface BP1_US of the first lower pattern BP1. Other ones of the first gate insulating films 130 may surround a corresponding one of the first sheet patterns NS1 with respect to a cross section (e.g., see FIG. 3). The first gate insulating films 130 may be disposed along the circumferences of the first sheet patterns NS1. Portions of the first gate electrode 120 may be disposed on the first gate insulating films 130. The first gate insulating films 130 may be disposed between portions of the first gate electrode 120 and the first sheet pattern NS1. Parts of the first gate insulating films 130 may be disposed between first sheet patterns NS1 that are adjacent to one another in the third direction D3 or between the first lower pattern BP1 and the first sheet patterns NS1.

The first gate insulating films 130 may be formed of and/or include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a greater dielectric constant than silicon oxide. The high-k material may include, for example, one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The first gate insulating films 130 are illustrated as being single homogenous films, but the present invention is not limited thereto. Each of the first gate insulating films 130 may include a plurality of films. The first gate insulating films 130 may include interfacial films, which are disposed between the first sheet patterns NS1 and the first gate electrodes 120, and high-k insulating films.

The semiconductor device according to some embodiments of the present disclosure may include negative capacitance (NC) FETs using negative capacitors. For example, the first gate insulating films 130 may include ferroelectric material films having ferroelectric properties and paraelectric material films having paraelectric properties.

The ferroelectric material films may have a negative capacitance, and the paraelectric material films may have a positive capacitance. For example, if two or more capacitors are connected in series and have positive capacitance, the total capacitance of the two or more capacitors may be lower than the capacitance of each of the two or more capacitors. On the contrary, if at least one of the two or more capacitors has negative capacitance, the total capacitance of the two or more capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of (and/or at least one of) the two or more capacitors.

If the ferroelectric material films having a negative capacitance and the paraelectric material films having a positive capacitance are connected in series, the total capacitance of the ferroelectric material films and the paraelectric material films may increase. Accordingly, transistors having the ferroelectric material films can have a sub-threshold swing (SS) of less than 60 mV/decade at room temperature.

The ferroelectric material films may have ferroelectric properties. The ferroelectric material films may be formed of and/or include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In some examples, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). In another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

The ferroelectric material films may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), silicon, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium, scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant may vary depending on the type of material of the ferroelectric material films.

If the ferroelectric material films include hafnium oxide, the dopant of the ferroelectric material films may include, for example, at least one of Gd, Si, Zr, Al, and Y.

If the dopant of the ferroelectric material films is Al, the ferroelectric material films may include 3 atomic % (at %) to 8 at % of Al. Here, the ratio of the dopant in the ferroelectric material films may refer to the ratio of the sum of the amounts of Hf and Al to the amount of Al in the ferroelectric material films.

If the dopant of the ferroelectric material films is Si, the ferroelectric material films may include 2 at % to 10 at % of Si. If the dopant of the ferroelectric material films is Y, the ferroelectric material films may include 2 at % to 10 at % of Y. If the dopant of the ferroelectric material films is Gd, the ferroelectric material films may include 1 at % to 7 at % of Gd. If the dopant of the ferroelectric material films is Zr, the ferroelectric material films may include 50 at % to 80 at % of Zr.

The paraelectric material films may include paraelectric properties. The paraelectric material films may be formed of and/or include, for example, at least one of silicon oxide and a high-k metal oxide. The high-k metal oxide may be and/or formed of include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but the present invention is not limited thereto.

The ferroelectric material films and the paraelectric material films may be formed of and/or include the same material. The ferroelectric material films may have ferroelectric properties, but the paraelectric material films may not have ferroelectric properties. For example, if the ferroelectric material films and the paraelectric material films include hafnium oxide, the hafnium oxide included in the ferroelectric material films may have a different crystalline structure from the hafnium oxide included in the paraelectric material films.

The ferroelectric material films may be thick enough to exhibit ferroelectric properties. The ferroelectric material films may have a thickness of, for example, 0.5 nm to 10 nm, but the present invention is not limited thereto. A critical thickness that can exhibit ferroelectric properties may vary depending on the type of ferroelectric material, and thus, the thickness of the ferroelectric material films may vary depending on the type of ferroelectric material included in the ferroelectric material films.

For example, each of the first gate insulating films 130 may include only one ferroelectric material film. In another example, each of the first gate insulating films 130 may include a plurality of ferroelectric material films that are spaced apart from one another. Each of the first gate insulating films 130 may have a structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

The first gate spacers 140 may be disposed on sidewalls of the first gate electrode 120. The first gate spacers 140 may not be disposed between the first lower pattern BP1 and first sheet patterns NS1 that are adjacent to one another in the third direction D3 and between the first sheet patterns NS1.

As shown in FIG. 4, the first gate spacers 140 may include inner sidewalls 140_ISW, connecting sidewalls 140_CSW, and outer sidewalls 140_OSW. The inner sidewall 140_ISW of the first gate spacers 140 may face a corresponding sidewall of a first gate electrode 120 that extends in the second direction D2. The inner sidewalls 140_ISW of the first gate spacers 140 may extend in the second direction D2 (e.g., extend along a corresponding sidewall of a first gate electrode 120). The inner sidewalls 140_ISW of the first gate spacers 140 may be opposite to the outer sidewalls 140_OSW of the first gate spacers 140 that face the interlayer insulating films 190. The connecting sidewalls 140_CSW of the first gate spacers 140 may connect the inner sidewalls 140_ISW of the first gate spacers 140 and the outer sidewalls 140_OSW of the first gate spacers 140. The connecting sidewalls 140_CSW of the first gate spacers 140 may extend in the first direction D1.

The first gate insulating films 130 may extend along the inner sidewalls 140_ISW of the first gate spacers 140. The first gate insulating films 130 may be interposed between in contact with a corresponding inner sidewall 140_ISW of a first gate spacers 140 and a corresponding first gate spacer 140).

The first gate spacers 140 may be formed of and/or include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO₂), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and a combination thereof. The first gate spacers 140 are illustrated as being a single homogenous film, but the present invention is not limited thereto.

The first gate capping patterns 145 may be disposed on the first gate electrodes 120 and the first gate spacers 140. The upper surfaces of the first gate capping patterns 145 may be on the same plane as the upper surfaces of the interlayer insulating films 190. Alternatively, the first gate capping patterns 145 may be disposed between the first gate spacers 140.

The first gate capping patterns 145 may be formed of and/or include at least one of, for example, SiN, SiON, SiCN, SiOCN, and a combination thereof. The first gate capping patterns 145 may include a material having an etching selectivity with respect to the interlayer insulating films 190.

The first source/drain pattern 150 may be disposed on the first active pattern AP1. The first source/drain pattern 150 may be disposed on and contact the first lower pattern BP1. The first source/drain pattern 150 may be connected to the first sheet patterns NS1. The first source/drain pattern 150 may be in contact with the first sheet patterns NS1.

As illustrated in FIG. 2, a first source/drain pattern 150 may be disposed on sides of adjacent first gate structures GS1. The first source/drain pattern 150 may be disposed between the first gate structures GS1, which are adjacent to each other in the first direction D1. For example, the first source/drain pattern 150 may be disposed on facing sides of adjacent first gate structures GS1. Alternatively, the first source/drain pattern 150 may be disposed on one side of only one of the first gate structures GS1.

The first source/drain patterns 150 may form the sources/drains of transistors that use the first sheet patterns NS1 as channel regions.

The first source/drain patterns 150 may be disposed in corresponding first source/drain recesses 150R. Each first source/drain pattern 150 may fill a first source/drain recess 150R.

The first source/drain recesses 150R may extend in the third direction D3. The first source/drain recesses 150R may be defined between the first gate structures GS1, which are adjacent to each other in the first direction D1.

The bottom surfaces of the first source/drain recesses 150R are defined by the first lower pattern BP1. The sidewalls of each of the first source/drain recesses 150R may be defined by the first sheet patterns NS1 and the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1). The inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) may define parts of the sidewalls of each of the first source/drain recesses 150R. Referring to FIG. 4, the first source/drain recess 150R is defined by the connecting sidewalls 140_CSW of the first gate spacers 140.

The inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) may have upper surfaces that face the bottom surfaces NS1_BS of the first sheet patterns NS1. The inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) may have bottom surfaces that faces the upper surfaces NS1_US of the first sheet patterns NS1 or the upper surface BP1_US of the first lower pattern BP1. The inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) may include sets of sidewalls that connect the upper surfaces and the bottom surfaces of the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1). The sidewalls of each of the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) may define parts of the sidewalls of each of the first source/drain recesses 150R.

The boundaries between the first gate insulating films 130 and the first lower pattern BP1 may correspond to the upper surface BP1_US of the first lower pattern BP1, between the first lower pattern BP1 and lowermost first sheet patterns NS1. The upper surface BP1_US of the first lower pattern BP1 may correspond to the boundaries between the first lower pattern BP1 and third inner gate structures INT3_GS1. The bottom surfaces of the first source/drain recesses 150R may be lower than the upper surface BP1_US of the first lower pattern BP1.

Referring to FIG. 2, each of the first source/drain recesses 150R may have wavy sidewalls (e.g., sidewalls having a series of convex protrusions arranged in the third direction D3 forming indented portions (e.g., concave portions) of the sidewalls therebetween). Each of the first source/drain recesses 150R may include a plurality of width-expanded regions 150R_ER. The width-expanded regions 150R_ER may be defined above the upper surface BP1_US of the first lower pattern BP1.

Each of the width-expanded regions 150R_ER may be vertically positioned (in the D3 direction) between a corresponding pair of first sheet patterns NS1 that are adjacent to each other in the third direction D3. The lowermost one of the width-expanded regions 150R_ER may be vertically positioned between the first lower pattern BP1 and the first sheet patterns NS1. Each of the width-expanded regions 150R_ER may vertically extend between two adjacent first sheet patterns NS1 in the third direction D3. Each of the width-expanded regions 150R_ER may be extend between a corresponding pair of inner gate structures that are adjacent to each other in the first direction D1.

Each of the width-expanded regions 150R_ER may include a portion whose width in the first direction D1 increases away from the upper surface BP1_US of the first lower pattern BP1 and a portion whose width in the first direction D1 decreases away from the upper surface BP1_US of the first lower pattern BP1. For example, the width of the width-expanded regions 150R_ER may increase and then decrease with respect to a direction away from the upper surface BP1_US of the first lower pattern BP1.

Points where the width of the width-expanded regions 150R_ER reaches its maximum may be located in the vertical (D3) direction between the first lower pattern BP1 and the first sheet patterns NS1 and between first sheet patterns NS1 that are adjacent to one another in the third direction D3.

The first source/drain pattern 150 may be in contact with the first sheet patterns NS1 and the first lower pattern BP1. Parts of the first source/drain pattern 150 may be in contact with the connecting sidewalls 140_CSW of the first gate spacers 140. The first gate insulating films 130 of the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1) may be in contact with the first source/drain pattern 150.

The first source/drain patterns 150 may include first lower semiconductor liners 151, first upper semiconductor liners 152, and a first filling semiconductor film 153.

The first lower semiconductor liner 151 may be continuously formed along the surface of (i.e., defining) the first source/drain recesses 150R. The first lower semiconductor liner 151 may extend along the sidewalls and the bottom surface of the first source/drain recess 150R. First lower semiconductor liners 151 may have a U-shape with respect to a cross section view (e.g., see FIG. 2).

The first lower semiconductor liner 151 may be in contact with the first sheet patterns NS1, the first lower pattern BP1, and the first gate insulating films 130 of the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1).

The first lower semiconductor liner 151 may include outer sidewalls 151_OSW and inner sidewalls 151_ISW. The outer sidewalls 151_OSW of the first lower semiconductor liners 151 may be in contact with the first gate insulating films 130, the first sheet patterns NS1, and the first lower pattern BP1. The outer sidewalls 151_OSW of the first lower semiconductor liner 151 may be in contact with the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1). The outer sidewalls 151_OSW of the first lower semiconductor liners 151 may exhibit the profile of the first source/drain recesses 150R with respect to a cross sectional view.

The inner sidewalls 151_ISW of the first lower semiconductor liners 151 may be opposite to the outer sidewalls 151_OSW of the first lower semiconductor liners 151. The first lower semiconductor liner 151 may include portions whose width in the second direction D2 decrease with respect to a direction away from the outer sidewalls 151_OSW of the first lower semiconductor liners 151. The inner sidewalls 151_ISW of the first lower semiconductor liner 151 may include facet portions and connecting portions. The facet portions of the inner sidewalls 151_ISW of the first lower semiconductor liner 151 may extend from the connecting sidewalls 140_CSW of the first gate spacers 140. The connecting portions of the inner sidewalls 151_ISW of the first lower semiconductor liner 151 may extend in the second direction D2.

For example, the first lower semiconductor liner 151 may include liner portions and protruding portions. Referring to FIG. 5, the liner portions of the first lower semiconductor liners 151 may be divided from the protruding portions of the first lower semiconductor liners 151 along a line connecting ends of first sheet patterns NS1 that are stacked in the third direction D1.

The liner portions of the first lower semiconductor liner 151 may extend along the sidewalls and the bottom surface of each of the first source/drain recesses 150R. The protruding portions of the first lower semiconductor liner 151 may protrude from the liner portions of the first lower semiconductor liner 151 in the first direction D1. The protruding portions of the first lower semiconductor liners 151 may protrude toward the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1). The protruding portions of the first lower semiconductor liner 151 may be in contact with the first gate insulating films 130 of the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1).

The first upper semiconductor liners 152 are disposed on corresponding first lower semiconductor liners 151. The first upper semiconductor liners 152 may extend along the sidewalls and the bottom surface of each of the first source/drain recesses 150R. The first upper semiconductor liners 152 may be formed along the profile of the first lower semiconductor liners 151.

The first upper semiconductor liners 152 may be disposed on the inner sidewalls 151_ISW of the first lower semiconductor liners 151. For example, the first upper semiconductor liners 152 may be in contact with the inner sidewalls 151_ISW of the first lower semiconductor liners 151.

The first upper semiconductor liners 152 may cover the entire inner sidewalls 151_ISW of the first lower semiconductor liners 151. The first upper semiconductor liners 152 may cover the facet portions and the connecting portions of the inner sidewalls 151_ISW of the first lower semiconductor liners 151. The first upper semiconductor liners 152 may be in contact with the connecting sidewalls 140_CSW of the first gate spacers 140.

The first filling semiconductor film 153 is disposed on the first upper semiconductor liners 152. The first filling semiconductor film 153 may fill the first source/drain recesses 150R. For example, the first filling semiconductor film 153 may be in contact with the first upper semiconductor liners 152.

The first lower semiconductor liners 151 may be formed of and/or include, for example, Si or SiGe. The first lower semiconductor liners 151 may be a crystalline semiconductor material, such as epitaxial semiconductor films. The first lower semiconductor liners 151 may be and/or include Si films or SiGe films.

The first upper semiconductor liners 152 may be and/or include, for example, Si or SiGe. The first upper semiconductor liners 152 may be a crystalline semiconductor material, such as epitaxial semiconductor films. The first upper semiconductor liners 152 may be and/or include Si films or SiGe films.

In a case where the first lower semiconductor liners 151 are SiGe, the Ge fraction of the first lower semiconductor liners 151 may be less than 10%. Also, in a case where the first upper semiconductor liner 152 are SiGe, the Ge fraction of the first upper semiconductor liners 152 may be less than 10%.

The first upper semiconductor liners 152 may be doped with carbon (C). The first upper semiconductor liners 152 may be epitaxial semiconductor layers doped with C. In a case where the first upper semiconductor liners 152 include Si films, the first upper semiconductor liners 152 may be Si films doped with C. In a case where the first upper semiconductor liners 152 include SiGe films, the first upper semiconductor liners 152 may be SiGe films doped with C. Less than 0.5 at % of C may be included in the first upper semiconductor liners 152, but the present invention is not limited thereto. In some examples, the C concentration of the first upper semiconductor liners 152 may be less than 2.5 E20 (2.5×10²⁰) (/cm³).

In a case where the first upper semiconductor liners 152 are doped with C, the resistance of the first upper semiconductor liners 152 against etching can be improved as compared to semiconductor films that are not doped with C. For example, referring to FIG. 30, the first upper semiconductor liners 152 may not be etched while first sheet patterns NS1 are being formed by removing sacrificial patterns SC_L. As the first upper semiconductor liners 152 cover the facet portions of the inner sidewalls 151_ISW of the first lower semiconductor liners 151, the penetration of an etchant for removing the sacrificial patterns SC_L, through the connecting sidewalls 140_CSW of the first gate spacers 140, can be prevented. The first upper semiconductor liners 152 can prevent the first filling semiconductor film 153 from being etched by the etchant. The etchant may be a gas or a liquid.

The first lower semiconductor liners 151 may form C-undoped regions 151_CUR. The C-undoped regions 151_CUR may be in contact with the first gate insulating films 130 of the inner gate structures (INT1_GS1, INT2_GS1, and INT3_GS1).

The first lower semiconductor liners 151 may not be doped with C and may not include C. Referring to FIGS. 5 and 6, the entire first lower semiconductor liners 151 may form the C-undoped regions 151_CUR. The C-undoped regions 151_CUR may be a crystalline semiconductor material, such as epitaxial semiconductor films that are not doped with C. As illustrated in FIG. 6, some of the C doped into the first upper semiconductor liners 152 may diffuse into the first filling semiconductor film 153.

In a case where the first source/drain pattern 150 is an NMOS source/drain (i.e., the source/drain of an NMOS transistor), the first filling semiconductor film 153 may be doped with a first n-type impurities (a charge carrier impurity). For example, the first filling semiconductor film 153 may be Si doped with a first n-type impurities. The first n-type impurities may be, for example, P (phosphorus), As (arsenic), Sb (antimony) and Bi (bismuth).

In some examples, n-type impurities may not be provided during the formation of the first lower semiconductor liners 151 and the first upper semiconductor liners 152 (e.g., no charge carrier impurities may be provided (directly or otherwise) to first lower semiconductor liners 151 and the first upper semiconductor liners 152 prior to the formation of first filling semiconductor film 153). Referring to FIG. 7, after formation of the first filling semiconductor film 153, the first n-type impurities included in the first filling semiconductor film 153 may diffuse into the first lower semiconductor liners 151 and the first upper semiconductor liners 152. The concentration of n-type impurities may gradually decrease with respect to a distance away from the first filling semiconductor film 153.

Alternatively, the first upper semiconductor liners 152 may include the diffused n-type impurities, but the first lower semiconductor liners 151 may not include the diffused n-type impurities.

In another example, the n-type impurities may not be provided during the formation of the first lower semiconductor liners 151, but may be provided with the formation of the first upper semiconductor liners 152. The n-type impurities may include at least one of P, As, Sb, and bismuth (Bi). In this example, the concentration of n-type impurities in the first upper semiconductor liners 152 may not gradually decrease away from the first filling semiconductor film 153.

In a case where the first source/drain pattern 150 is included in a PMOS source/drain, the first filling semiconductor film 153 may be epitaxial SiGe doped with p-type impurities. For example, the p-type impurities may be B, but the present invention is not limited thereto. The Ge fraction of the first filling semiconductor film 153 may be greater than the Ge fractions of the first lower semiconductor liner 151 and the first upper semiconductor liners 152.

For example, the p-type impurities may be provided during the formation of the first lower semiconductor liners 151 and the first upper semiconductor liners 152 (e.g., prior to forming the first filling semiconductor film 153). The first lower semiconductor liners 151 and the first upper semiconductor liners 152 may include doped B. The concentration of p-type impurities in the first lower semiconductor liners 151 may differ from the concentration of p-type impurities in the first upper semiconductor liners 152 and the concentration of p-type impurities in the first filling semiconductor film 153, but the present invention is not limited thereto. The concentration of p-type impurities in the first upper semiconductor liners 152 may differ from the concentration of p-type impurities in the first filling semiconductor film 153, but the present invention is not limited thereto.

In another example, the p-type impurities may be provided during the formation of the first lower semiconductor liners 151, but not during the formation of the first upper semiconductor liners 152 (which may be formed undoped of charge carrier dopants).

The source/drain etch stopper films 185 may extend along the profiles of the outer sidewalls 140_OSW Of the first gate spacers 140 and the first source/drain pattern 150. Although not specifically illustrated, the source/drain etch stopper films 185 may be disposed on the upper surface of the field insulating film 105.

The source/drain etch stopper films 185 may include a material having an etching selectivity with respect to the first interlayer insulating films 190. The source/drain etch stopper films 185 may be and/or include at least one of, for example, SiN, SiON, SiOCN, SiBN, SiOBN, SiOC, and a combination thereof.

The first interlayer insulating films 190 may be disposed on the source/drain etch stopper films 185. The first interlayer insulating films 190 may be disposed on the first source/drain pattern 150. The first interlayer insulating films 190 may not cover the upper surfaces of the first gate capping patterns 145. For example, the upper surfaces of the first interlayer insulating films 190 may be on the same plane as the upper surfaces of the first gate capping patterns 145.

The first interlayer insulating films 190 may be and/or include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocycloutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonen silazen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoam (such as polypropylene oxide), carbon doped silicon oxide (CDO), organo silicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, and a combination thereof, but the present invention is not limited thereto.

The first source/drain contacts 180 are disposed on the first source/drain pattern 150. The first source/drain contacts 180 are connected to the first source/drain pattern 150. The first source/drain contacts 180 may be connected to the first source/drain pattern 150 through the first interlayer insulating films 190 and the source/drain etch stopper films 185.

First metal silicide films 155 may be further disposed between the first source/drain contacts 180 and the first source/drain pattern 150.

The first source/drain contacts 180 are illustrated as being single homogenous film, but the present invention is not limited thereto. The first source/drain contacts 180 may be formed of one or more of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

The first metal silicide films 155 may be formed of a metal silicide.

A second interlayer insulating film 191 is disposed on the first interlayer insulating films 190. The second interlayer insulating film 191 may be formed of one or more of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

The wiring 205 (a conductive wire formed of one or more conductors) is disposed in the second interlayer insulating film 191. The wiring 205 may be connected to the first source/drain contacts 180. The wiring 205 may include a wiring line 207 and a wiring via 206.

In some examples, the wiring via 206 may be formed in one deposition process (e.g., a first damascene process), and then, the wiring line 207 may be formed in a second deposition process (e.g., a second damascene process). In some examples, the wiring via 206 and wiring line 207 may be formed of different materials from one another. In other examples, the wiring via 206 and the wiring line 207 may be formed at the same time (e.g., in a single deposition process and formed of the same material).

The wiring line 207 and the wiring via 206 may are each illustrated as being single homogenous film, but the present invention is not limited thereto. The wiring line 207 and the wiring via 206 may be formed of one or more of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material.

For example, the upper surface of a first source/drain contact 180 connected to the wiring 205 may be on the same plane as the upper surface of a first source/drain contact 180 not connected to the wiring 205.

FIG. 9 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 10 is a graph showing the concentration of C along the scan line “SCAN LINE” of FIG. 9. For convenience, the embodiment of FIGS. 9 and 10 will hereinafter be described, focusing mainly on the differences with the embodiment of FIGS. 1 through 8. Specifically, FIG. 9 is an enlarged cross-sectional view of part P (of FIG. 2) of a semiconductor device according to some embodiments of the present disclosure.

Referring to FIGS. 9 and 10, a first lower semiconductor liner 151 may include a C-undoped region 151 and a C-diffused region 151_CDR.

The C-diffused region 151_CDR may be part of the first lower semiconductor liner 151 where some of the C that was doped into the first upper semiconductor liner 152 has diffused. The concentration of C in the C-diffused region 151_CDR may increase with respect to an increase in distance away from the C-undoped region 151_CUR. In other words, the concentration of C in the C-diffused region 151_CDR decreases with respect to an increase in distance away from a first filling semiconductor film 153. Alternatively, the first filling semiconductor film 153 may not include diffused C (such as C diffused from the first upper semiconductor liner 152).

For example, the C-undoped region 151_CUR may extend along the sidewalls and the bottom surface of a first source/drain recess 150R. The C-undoped region 151_CUR may be continuously formed along the sidewalls and the bottom surface of the first source/drain recess 150R.

The C-diffused region 151_CDR is disposed between the first upper semiconductor liner 152 and the C-undoped region 151_CUR. The C-diffused region 151_CDR may extend along the sidewalls and the bottom surface of the first source/drain recess 150R. The C-diffused region 151_CDR may be part of a liner portion of the first lower semiconductor liner 151. In other words, the C-diffused region 151_CDR may not be in contact with the ends of the first sheet patterns NS1.

The C-undoped region 151_CUR may be in contact with first gate insulating films 130 of first and second inner gate structures INT1_GS1 and INT2_GS1. The C-diffused region 151_CDR may not be in contact with the first gate insulating films 130 of the first and second inner gate structures INT1_GS1 and INT2_GS1.

FIG. 11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. For convenience, the embodiment of FIG. 11 will hereinafter be described, focusing mainly on the differences with the embodiment of FIGS. 9 and 10. Specifically, FIG. 11 is an enlarged cross-sectional view of part P (of FIG. 2) of a semiconductor device according to some embodiments of the present disclosure.

Referring to FIG. 11, a C-undoped region 151_CUR may not be continuously formed along the sidewalls and the bottom surface of a first source/drain recess 150R.

In a cross-sectional view, several C-undoped regions 151_CUR may be in the shape of islands that are spaced apart from one another. The C-undoped regions 151_CUR may comprise a plurality of sub-C-undoped regions that are spaced apart from one another in a third direction D3.

For example, the C-undoped region 151_CUR may include discrete first and second sub-C-undoped regions that are spaced apart from each other in the third direction D3 and separated from one another by the carbon doped region 151_CDR. The first sub-C-undoped region may not be directly connected to the second sub-C-undoped region (the first and second sub-C-undoped regions are not part of a larger continuous C-undoped region). The first C-undoped region may be separated from the second sub-C-undoped region through a C-diffused region 151_CDR (which contacts both the first and second sub-C-undoped regions).

The C-diffused regions 151_CDR may be in contact with the ends of first sheet patterns NS1. For example, the C-diffused region 151_CDR may not be in contact with first gate insulating films 130 of first and second inner gate structures INT1_GS1 and INT2_GS1.

Alternatively, parts of the first and second inner gate structures INT1_GS1 and INT2_GS1 may be in contact with the C-diffused region 151_CDR.

FIG. 12 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 13 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 14 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. For convenience, the embodiments of FIGS. 12 through 14 will hereinafter be described, focusing mainly on the differences with the embodiment of FIGS. 1 through 8. Specifically, FIGS. 12 through 14 are enlarged cross-sectional views of parts P (of FIG. 2) of semiconductor devices according to some embodiments of the present disclosure.

Referring to FIG. 12, an entire first lower semiconductor liner 151 may be a C-diffused region 151_CDR.

The first lower semiconductor liner 151 may not include a C-undoped region (“151_CUR” of FIG. 11).

Referring to FIG. 13, the semiconductor device according to some embodiments of the present disclosure may further include semiconductor residue patterns SP_R, which are disposed between a first lower semiconductor liner 151 and inner gate structures (as shown with respect to first and second inner gate structures INT1_GS1 and INT2_GS1). It should be understood that such semiconductor residue patterns SP_R may be formed with respect to other of the embodiments described herein.

The semiconductor residue patterns SP_R may be in contact with first sheet patterns NS1. The semiconductor residue patterns SP_R may be in contact with an outer sidewall (“151_OSW” of FIG. 4) of the first lower semiconductor liner 151 and sidewalls of the first and second inner gate structures INT1_GS1 and INT2_GS1.

The semiconductor residue patterns SP_R may include, for example, SiGe. In a case where the first lower semiconductor liner 151 includes SiGe, the Ge fraction of the semiconductor residue patterns SP_R may be greater than the Ge fraction of the first lower semiconductor liner 151. The semiconductor residue patterns SP_R may be parts of sacrificial patterns (“SC_L” of FIG. 29) that remain unremoved.

Referring to FIG. 14, the semiconductor device according to some embodiments of the present disclosure may further include inner gate airgaps INT_AG, which are disposed between a first lower semiconductor liner 151 and first and second inner gate structures INT1_GS1 and INT2_GS1. It should be understood that such inner gate airgaps INT_AG may be formed with respect to other of the embodiments described herein (although the formation of both inner gate airgaps INT_AG and semiconductor residue patterns SP_R described with respect to FIG. 13 may result in smaller sizes of both).

The inner gate airgaps INT_AG may be disposed between the first lower semiconductor liner 151 and first gate insulating films 130 of the first and second inner gate structures INT1_GS1 and INT2_GS1. The inner gate airgaps INT_AG may be defined between the first lower semiconductor liner 151, first sheet patterns NS1, and the first and second inner gate structures INT1_GS1 and INT2_GS1.

Although not specifically illustrated, in a case where the first gate insulating films 130 include interfacial films and high-k insulating films, the interfacial films may be formed on parts of the first lower semiconductor liner 151 that are in contact with the inner gate airgaps INT_AG.

FIGS. 15 and 16 illustrate a semiconductor device according to some embodiments of the present disclosure. The embodiment of FIGS. 15 and 16 will hereinafter be described, focusing mainly on the differences with the embodiment of FIGS. 1 through 8. Specifically, FIG. 15 is a cross-sectional view, taken along line A-A of FIG. 1, of a semiconductor device according to some embodiments of the present disclosure, and FIG. 16 is a plan view, taken along line C-C of FIG. 15, of the semiconductor device of FIG. 15.

Referring to FIGS. 15 and 16, a first source/drain pattern 150 may further include an inserted semiconductor liner 154, which is disposed between a first upper semiconductor liner 152 and a first filling semiconductor film 153.

The inserted semiconductor liner 154 may extend along the boundary between the first upper semiconductor liner 152 and the first filling semiconductor film 153.

In a case where the first source/drain pattern 150 is included in an NMOS source/drain, the inserted semiconductor liner 154 may be doped with second n-type impurities. The inserted semiconductor liner 154 may be Si doped with second n-type impurities. For example, the second n-type impurities may be different from the first n-type impurities doped in the first filling semiconductor film 153 (i.e., the second n-type impurities may not be doped in the first filling semiconductor film 153 and the first n-type impurities may not be doped in the inserted semiconductor liner 154). In some examples, the first n-type impurity may be P and the second n-type impurities may include at least one of As, Sb, and Bi. For example, the inserted semiconductor liner 154 may include a Si film doped with As.

In a case where the first source/drain pattern 150 is included in a PMOS source/drain, the inserted semiconductor liner 154 may include SiGe doped with p-type impurities. The Ge fraction of the first filling semiconductor film 153 may be greater than the Ge fraction of the inserted semiconductor liner 154. In a case where the first upper semiconductor liner 152 includes SiGe, the Ge fraction of the inserted semiconductor liner 154 may be greater than the Ge fraction of the first upper semiconductor liner 152.

FIGS. 17 through 19 are cross-sectional views of semiconductor devices according to some embodiments of the present disclosure. FIGS. 20 and 21 are cross-sectional views of semiconductor devices according to some embodiments of the present disclosure. For convenience, the embodiments of FIGS. 17 through 21 will hereinafter be described, focusing mainly on the differences with the embodiment of FIGS. 1 through 8.

Referring to FIG. 17, a first source/drain pattern 150 may include stacking faults 150_SF. It should be understood that these stacking faults 150_SF may be provided with (to modify) any of the embodiments described herein.

The stacking faults 150_SF are disposed in a first filling semiconductor film 153. In a cross-sectional view, the stacking faults 150_SF may be inclined in a direction from first gate spacers 140 to a first lower pattern BP1.

Referring to FIG. 18, a first source/drain pattern 150 may include source/drain airgaps 150_AG. It should be understood that these airgaps 150_AG may be provided with (to modify) any of the embodiments described herein.

The source/drain airgaps 150_AG are disposed in a first filling semiconductor film 153.

Referring to FIG. 19, each of first source/drain recesses 150R does not include width-expanded regions (“150R_ER” of FIG. 2).

Each of first source/drain recesses 150R does not have wavy sidewalls. The width of upper parts of the sidewalls of each of the first source/drain recesses 150R may decrease away from a first lower pattern BP1. It should be understood that other embodiments described herein may be similarly modified to not include the width-expanded regions and/or to not have wavy sidewalls.

Referring to FIG. 20, the upper surface of a first source/drain contact 180 not connected to a wiring 205 may be lower than the upper surfaces of first gate capping patterns 145.

The upper surface of a first source/drain contact 180 connected to the wiring 205 may be higher than the upper surface of the first source/drain contact 180 not connected to the wiring 205. It should be understood that other embodiments described herein may be similarly modified to include features of FIG. 20.

Referring to FIG. 21, each of first source/drain contacts 180 may include a lower source/drain contact 181 and an upper source/drain contact 182.

The upper source/drain contact 182 may be disposed in a first source/drain contact 180 connected to a wiring 205. On the contrary, the upper source/drain contact 182 may not be disposed in a first source/drain contact 180 not connected to the wiring 205.

A wiring line 207 may be connected to the first source/drain contacts 180 without the aid of a wiring via (“206” of FIG. 2). The wiring 205 may not include a wiring via (“206” of FIG. 2).

The lower source/drain contact 181 and the upper source/drain contact 182 are illustrated as being single homogenous films, but the present invention is not limited thereto. The lower source/drain contact 181 and the upper source/drain contact 182 may be formed of one or more of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material. It should be understood that other embodiments described herein may be similarly modified to include features of FIG. 21.

FIGS. 22 and 23 illustrate a semiconductor device according to some embodiments of the present disclosure. Specifically, FIG. 22 is a plan view of a semiconductor device according to some embodiments of the present disclosure, and FIG. 23 is a cross-sectional view taken along line D-D of FIG. 22.

A cross-sectional view, taken along line A-A, of the semiconductor device of FIG. 22 may be as illustrated in any one of FIGS. 2, 15, and 17 through 29. A first region I of FIG. 22 may be the same as the NMOS region embodiments described above with reference to FIGS. 1 through 19, and thus, a second region II of FIG. 22 will hereinafter be described in detail.

Referring to FIGS. 22 and 23, the semiconductor device according to some embodiments of the present disclosure may include a first active pattern AP1, a plurality of first gate structures GS1, a first source/drain pattern 150, a second active pattern AP2, a plurality of second gate structures GS2, and a second source/drain pattern 250.

A substrate 100 may include the first and second regions I and II. The first region I may be a region where an NMOS is formed, and the second region II may be a region where a PMOS is formed.

The first active pattern AP1, the first gate structures GS1, and the first source/drain pattern 150 may be disposed in the first region I of the substrate 100. The second active pattern AP