f are planarized.

FIG. 2F illustrates an example of solder bumps formed by an implementation of optimized solder volume for flip-chip bonding in one embodiment. The resist shown in FIG. 2E can be removed or stripped in response to the deposition of solder into SROs 208, 209. In response to the removal, a structure can be formed as shown in FIG. 2F. Solder bumps 212c, 212f are formed and standing on pads 106 on top surface 105.

FIG. 2G illustrates an example of a combination of a first substrate and a second substrate as a result of an implementation of optimized solder volume for flip-chip bonding in one embodiment. In the example shown in FIG. 2G, substrate 102 can be flip-chip mounted on substrate 104 by connecting pads 110 to solder bumps 212c, 212f. Upon the connection, a package can be formed as shown in FIG. 2H, where the connection causes solder bumps 212c, 212f to settle as solder joints, such as solder joints 216c, 216f. Solder joint 216c can connect pads 106c, 110c that are relatively closer to one another, and solder joint 216f can connect pads 106f, 110f that are relatively further from one another. Solder joints 216c, 216f can be of different sizes and can have optimized solder volume to prevent undesirable conditions such as electrical open joints and/or solder bridging.

FIG. 3A illustrates another example of a layer of resist with variable resist thickness in one embodiment. In an example shown in FIG. 3A, a layer of resist, labeled as resist layer 302, can be deposited on top surface 103 of substrate 102. Resist layer 302 can have variable thickness (e.g., vertical distance in z-direction from top surface 103 to peak of resist). In the example shown in FIG. 3A, one portion of resist layer 302 can have a thickness of T3, another portion of resist layer 302 can have a thickness of T4, and another portion of resist layer 302 can have a thickness of T5. T3 can be greater T4, and T4 can be greater than T5. In one embodiment, top surface 103 can be flat and thus the variable thickness of resist layer 302 define SROs having different sizes. In one embodiment, the different thicknesses of resist layer 302 across top surface 103 can be predetermined based on target solder volumes, such as target solder volumes 202, 204 in FIG. 2A.

In one embodiment, resist layer 302 can be formed by spin coating, such as dispensing liquid resist on substrate 102 then rotate substrate 102 at a specific rotational speed. In an aspect, resist layer formed by spin coating can have almost uniform thickness. To be described in more detail below, imitation pads can be added to top surface 103 to elevate the resist layer at certain locations, and pads can be removed from top surface 103 to lower the resist layer at certain locations. These adjustment to pads on top surface can cause variation in the thickness of the resist layer.

FIG. 3B illustrates another example of solder resist openings formed by a layer of resist with variable resist thickness in one embodiment. In an example shown in FIG. 3B, resist layer 302 in FIG. 3A can be etched to form a plurality of SROs, such as SROs 308, 309. SRO 308 can be defined or bounded by resists 302a, 302b, and pad 110f. In one embodiment, a mask and ultraviolet (UV) rays can be used for the resist patterning to form SROs 308, 309. The mask can have variable exposure levels such that the amount of resist removed from the top of pads 110c can be less than the amount of resist removed from the top of pads 110f. SRO 309 can be defined or bounded by resists 302d, 302e, and pad 110c. In response to the etching, resists 302a, 302b, 302c, and other resists, can remain on top surface 103. Resist 302a can have the thickness T3, resist 302b can have variable thickness including thickness T4, and resist 302c can have the thickness T5. Resist 302b may be deformed (e.g., not planarized) in order to have a variable thickness to form SROs of different sizes on the sides of resist 302b. For example, to form an SRO 309 that is smaller than SRO 308, resist 302b can have a slanted peak downwards towards pads 110c. SROs 308, 309 can comply with target solder volumes 202, 204 shown in FIG. 2A, such as having sufficient capacity to hold solder at target solder volumes 202, 204 without overflowing or unfilled portions. In the embodiment shown in FIG. 3B, a diameter or width (e.g., spanning −x to x direction) of SROs 308, 309 can be same as a diameter of pads 110.

In another embodiment, the resist patterning can be performed prior to disposing pads 110 on top surface 103. For example, resist 302a, 302b, 302c can be formed by resist patterning using the mask with variable exposure, then pads 110 can be formed by metal plating. The usage of a mask with variable exposure level can pattern a resist layer to different resists with different thickness.

FIG. 3C illustrates another example of solder deposited in the solder resist openings shown in FIG. 3B. In an example shown in FIG. 3C, solder can be deposited into SROs 308 in FIG. 3B to form solder bumps 310f, and solder can be deposited into SROs 309 in FIG. 3B to form solder bumps 310c. Solder can be deposited into SROs 308, 309 using, for example, injection of molten solder (IMS) or solder paste printing techniques. Solder bumps 310c, 310f can have different solder volumes. Further, solder bumps 310c, 310f can have the same, or approximately the same, volumes as target solder volume 202, 204, respectively, shown in FIG. 2A.

FIG. 3D illustrates another example of solder bumps formed by an implementation of optimized solder volume for flip-chip bonding in one embodiment. Resist layer 302 in FIG. 3B can be removed or stripped, resulting in a structure shown in FIG. 3D. In FIG. 3D, solder bumps 310c, 310f are formed and standing on pads 110 on top surface 103. Solder bumps 310c, 310f can be formed with solder volume that is the same, or approximately the same, as target solder volumes 202, 204 in FIG. 2A.

FIG. 3E illustrates another example of a combination of a first substrate and a second substrate as a result of an implementation of optimized solder volume for flip-chip bonding in one embodiment. In the example shown in FIG. 3E, substrate 102 can be flip-chip mounted on substrate 104 by connecting solder bumps formed on pads 110 to pads 106 of substrate 104. Upon the connection, a package can be formed as shown in FIG. 3F, where the connection causes solder bumps 310c, 310f to settle as solder joints. The solder joints formed can be of different sizes and can have optimized solder volume to prevent undesirable conditions such as electrical open joints and/or solder bridging.

FIG. 4A illustrates another example of solder bumps formed by an implementation of optimized solder volume for flip-chip bonding in one embodiment. In an example shown in FIG. 4A, solder bumps 402 having uniform size can be formed on pads 110 of substrate 102, and solder bumps having different sizes, such as solder bumps 404, 406, can be formed on pads 106 of substrate 104. A resist layer having uniform thickness can be used for forming solder bumps 402 on pads 110 of substrate 102. A resist layer having variable thickness can be used for forming solder bumps 404, 406 on pads 106 of substrate 104. Substrate 102 can be flip-chip mounted on substrate 104 by connecting solder bumps 402 formed on pads 110 to solder bumps 404, 406 formed on pads 106. Upon the connection, a combination of solder bumps 402, 404 can result in a solder joint having volume that can be the same, or approximately the same, as target solder volume 202 in FIG. 2A. A combination of solder bumps 402, 406 can result in a solder joint having volume that can be the same, or approximately the same, as target solder volume 204 in FIG. 2A.

FIG. 4B illustrates another example of solder bumps formed by an implementation of optimized solder volume for flip-chip bonding in one embodiment. In an example shown in FIG. 4B, solder bumps 410 having uniform size can be formed on pads 110 of substrate 102, and solder bumps 412 having same or different sizes can be formed on a portion of pads 106 of substrate 104. In the example shown in FIG. 4B, solder bumps 412 can be formed on pads 106 with peaks that are relatively shorter, such as pads 106f. No solder bumps are formed on pads 106 with peaks that are relatively taller, such as pads 106c. A resist layer having uniform thickness can be used for forming solder bumps 410 on pads 110 of substrate 102. A resist layer having variable thickness can be used for forming solder bumps 412 on pads 106f of substrate 104. Substrate 102 can be flip-chip mounted on substrate 104 by connecting solder bumps 410 formed on pads 110 to pads that has no solder bumps (e.g., pads 106c) and solder bumps 412 formed on pads 106f. Upon the connection, a combination of solder bumps 410 with pads 106c can result in solder joints having volume that can be the same, or approximately the same, as target solder volume 202 in FIG. 2A. A combination of solder bumps 410 with solder bumps 412 can result in solder joints having volume that can be the same, or approximately the same, as target solder volume 204 in FIG. 2A.

FIG. 5A illustrates an example system 500 that can implement optimized solder volume for flip-chip bonding in one embodiment. System 500 can include a device 504 and a device 510. Device 504 can be configured to obtain a surface topology of top surface 105. In one embodiment, device 504 can be a laser sensor that can scan at least a portion of top surface 105 and generate two-dimensional (2D) and/or three-dimensional (3D) surface topologies of top surface 105. Device 510 can be a computing device including at least a processor 512 and a memory 514. Memory 514 can be configured to store instructions, such as program code (e.g., source code and/or executable code). Processor 512 can be configured to run or implement the instructions stored in memory 514 to perform the at least some of the operations described herein, such as determination of target solder volume (e.g., FIG. 2A), determination of resist thickness, determination of SROs, identification of portions of surfaces that need imitation pads or pads removed, determination of adjustments to exposure levels across different portions of a resist mask, and/or other operations described herein.

By way of example, device 504 can scan at least a portion, such as a portion 502, of top surface 105 of substrate 104 and generate surface topology data 506. Surface topology data 506 can be, for example, digital data (e.g., digital image data) representing a surface topology of portion 502 scanned by device 504. Device 504 can send surface topology data 506 to device 510. Device 504 can also scan at least a portion of top surface 103 of substrate 102 (see FIG. 1) and generate surface topology data for top surface 103, and can send the generated surface topology data for top surface 103 to device 510.

In one embodiment, processor 512 can determine a plurality of target solder volumes (e.g., see FIG. 2A). Each target solder volume can correspond to one pad among pads 106, and one pad among pads 110. Each target solder volume can be an amount of solder that can be used for bonding corresponding pads 106, 110 without electrical open joints and/or solder bridging. By way of example, processor 512 can be configured to simulate a flip-chip mounting process to mount substrate 102 to substrate 104. The simulation can show solder volume being used for bonding each pad 106 to a corresponding pad 110, pads 110 without electrical open joints and/or solder bridging. This solder volumes obtained from the simulation can be set as target solder volumes.

In another embodiment, processor 512 can perform a process to determine virtual planes and ideal heights for determining target solder volumes. By way of example, processor 512 can determine a first virtual plane 501A that is parallel to a stage being used for bonding substrate 102 and substrate 104. The first virtual plane 501A can have portions that can be lower than relatively taller pads (e.g., pads 106c in FIG. 2A) and portions that can be higher than relatively shorter pads (e.g., pads 106f in FIG. 2A). An ideal height of target solder volumes can be determined based on pad diameters and pitches. Different pad diameters and pitches can have different threshold solder volumes for electrical open joints and solder bridging. Lower limits of the ideal height can be a threshold where electrical open joints can occur, and upper limits of the ideal height can be a threshold where solder bridging can occur. Processor 512 can determine the ideal height and add the ideal height to first virtual plane 501A to determine a second virtual plane 501B. Processor 512 can determine target solder volumes by determining differences between each pad 106 and second virtual plane 501B.

Processor 512 can be configured to determine different thicknesses of different portions of a resist layer to be deposited across top surface 105. The different thicknesses can define a plurality of SROs having sizes that comply with the plurality of target solder volumes, such as having sufficient capacity to hold an amount of solder equivalent to the target solder volumes without electrical open joints and/or solder bridging. In one embodiment, processor 512 can determine a height (e.g., z-direction) and a diameter (e.g., x-direction) of each SRO to be formed on pads 106 in portion 502. Based on the determined height and/or diameter, processor 512 can determine different resist thicknesses of resist to be deposited on top surface 105 and in-between pads 106. Using FIG. 2C as an example, processor 512 can determine that in order to form SRO 208 that complies with target solder volume 202 in FIG. 2A, a portion of resist between two pads 106c needs a thickness of T1. Also, in order to form SRO 209 that complies with target solder volume 204 in FIG. 2A, a portion of resist between pads 106c and pad 106f needs a thickness of T2.

In one embodiment, processor 512 can determine the different thicknesses of resist across top surface 105 in a piecewise manner. Device 504 can scan different portions of top surface, such as scanning portion 502 and another portion 518 at different times. The surface topology data of portions 502, 518 can be provided to processor 512 as separate pieces of data. Processor 512 can perform a first determination of the different thicknesses for portion 502, and can perform a second determination of the different thicknesses for portion 518. The size of portions of top surface 105 to be scanned separately can be arbitrary.

In order to achieve the determined resist thickness during formation of a package based on variable resist thickness (e.g., package 100 in FIG. 1), processor 512 can use surface topology data received from device 504 to generate data that can be used by apparatuses that construct or form the package. In one embodiment, processor 512 can generate pad density adjustment data that indicates additions imitation pads and/or removal of pads from top surfaces 103, 105. In another embodiment, processor 512 can generate exposure adjustment data that indicates different exposure levels for different portions of a mask being used for performing resist patterning.

By way of example, processor 512 of device 510 can receive surface topology data 506 and use surface topology data 506 to determine a pad density of portion 502. Processor 512 of device 510 can also receive the surface topology data for top surface 103 and determine a pad density of top surface 103. In one or more embodiments, processor 512 can run instructions stored in memory 514 to perform various image processing techniques on images in surface topology data 506 in order to extract data necessary for determining pad densities.

FIG. 5B shows an example of an image 520 that can be included in surface topology data 506 generated by device 504. In an aspect, the surface topology of portion 502 of top surface 105 can indicate a surface topography, visually represented by an image 520, of portion 502. The surface topology can indicate attributes such as depth measurements between peaks of the plurality of pads 106 and top surface 105 (e.g., peak-to-valley depths along the z axis). The depth measurements indicated by the surface topology can reflect undulations across portions 502 of top surface 105. In the example shown in FIG. 5B, a shade 522 can represent a lowest (e.g., smallest z-value) height on scanned portion 502, a shade 526 can represent a highest (e.g., greatest z-value) height on scanned portion 502, and other shades, such as shade 524, can represent heights between the highest and lower heights on scanned portion 502.

FIG. 6A illustrates an example image that can be used in generation pad density adjustment data in one embodiment. In one embodiment, processor 512 can use surface topology data 506 and/or image 520 to determine a pad density of top surface 105 (see FIG. 5A). In an example shown in FIG. 6A, processor 512 can convert image 520 (FIG. 5B) into a pad density image 600. Pad density image 600 can be a digital image, such as bitmap data or raster image, showing a layout of pads on scanned portion 502. Processor 512 can be configured to determine whether portions of pad density image 600 has a pad density within a predetermined range of pad density thresholds. In response to a specific portion having a pad density within the range of predetermined pad density thresholds, processor 512 can identify the specific portion as a portion that does not need pad density adjustment. In response to a specific portion having a pad density greater than the greatest value in the range of predetermined pad density thresholds, processor 512 can identify the specific portion as a portion that needs pads removed to decrease its pad density. In response to a specific portion having a pad density less than the least value in the range of predetermined pad density thresholds, processor 512 can identify the specific portion as a portion that needs imitation pads added to increase its pad density.

Referring to pad density image 600, portions with relatively lower pad density, such as portions 602, 604, can have relatively thinner layer of resist if resist is being deposited on portion 502 without adjustment to pad density. Processor 512 can identify portions 602, 604 as portions that need an increase in pad density, and can generate pad density adjustment data indicating the need to add imitation pads in portions 602, 604 of top surface 105. Referring to FIG. 6B, the pad density adjustment data can indicate at least one imitation pad 606 can be added to portion 602, and at least one imitation pad 608 can be added to portion 604. The addition of imitation pads 606, 608 can increase a pad density of portions 602, 604. By adding imitation pads 606, 608 to increase pad density of portions 602, 604, resists being deposited on portions 602, 604 and surrounding areas can result in thicker resist. In some embodiments, pads can also be removed from portions that may be considered overly dense to reduce resist thickness. In another embodiment, processor 512 can identify portions 602, 604 as portions that need an increase in pad density, and can generate pad density adjustment data indicating the need to increase diameters of pads within a vicinity of (or surrounding) the identified portions 602, 604. The increased diameters of these pads can increase a pad density of portions 602, 604.

FIG. 6C illustrates a cross-sectional area of a portion that has relatively lower pad density in one embodiment. A portion of top surface 105 shown in FIG. 6C. This portion can have a relatively lower pad density, as shown by a relatively far distance between a pad 610 and a pad 612. Due to the lower pad density, a resist layer being formed on top surface 105 may be lowered at the portion between pads 610, 612. This lowered portion of the resist layer can result in SROs that do not comply with target solder volumes 202, 204. For example, an SRO to be formed on pad 610 can be bounded by a resist pattern having a thickness T1′, instead of a determined thickness T1 (see FIG. 2A). An SRO to be formed on pad 612 can be bounded by a resist pattern having a thickness T2′, instead of a determined thickness T2 (see FIG. 2A).

FIG. 6D illustrates a cross-sectional area of the portion in FIG. 6C with an addition of an imitation pad in one embodiment. In FIG. 6D, an imitation pad 616 is added to the portion shown in FIG. 6C. As a result of adding imitation pad 606, the resist layer between pads 610, 612 can be elevated and SROs being formed on top of pads 610, 612 can be bounded by resist patterns with the determined thicknesses T1, T2.

Therefore, processor 512 can be configured to use surface topology data 506 generated by device 504 to determine adjustment to resist thickness at different portions across top surface 105. Processor 512 can determine which portions on the scanned surface (e.g., portion 502) may need imitation pads to increase resist thickness, or which portions may need pads removed to reduce resist thickness. By using surface topology of top surface 105 to adjust resist thickness, the thickness of a resist layer being formed on top surface 105 can vary across top surface 105, and solder resist openings bounded by the resist layer can vary in size and/or dimensions as well. The varying solder resist openings can allow solder bumps with different sizes and/or dimensions, solder bumps that comply with target solder volumes, to be formed on pads 106.

FIG. 7A illustrates an example layout of a mask with variable exposure levels in one embodiment. A mask 700 is shown in FIG. 7A. In one embodiment, mask 700 can be a photomask, can be an opaque plate or film coated with transparent, patterned, or opaque areas. In another embodiment, mask 700 can be a grayscale mask having different areas with different intensity levels for modulating UV light rays. The different exposure levels being determined by processor 512 can be different intensity levels of the grayscale mask. Processor 512 can generate exposure level adjustment data that can be used for designing and manufacturing mask 700 with variable exposure levels.

In the example shown in FIG. 7A, mask 700 can include areas 704, 708 that has an exposure level of 100%. An exposure level of 100% can allow UV light rays to fully penetrate mask 700. Mask 700 can further include areas 702, 706, 714 having exposure level of 91%, and areas 710, 712 having exposure level of 84%. Exposure level of 91% can allow 91% of UV light rays to pass through mask 700, and exposure level of 84% can allow 84% of light rays to pass through mask 700.

Referring to FIG. 7B, as a result of using mask 700 with variable exposure levels, UV light rays 720 can pass through mask 700 through the areas with different exposure levels to form a resist layer with variable thickness on top surface 103 of substrate 102, where top surface 103 can be flat and have uniform pad density. In the example shown in FIG. 7B, mask 700 can include areas with different exposure levels, such as 100%, 80%, 60%, or other exposure levels. The example in FIG. 7B shows an implementation of using negative tone photoresist, such that exposure levels that are relatively higher can cause a smaller height reduction of resist materials when compared to lower exposure levels. Referring to FIG. 7C, as a result of the implementation shown in FIG. 7B, a resist layer having variable thickness can be formed. The variable exposure levels causes a different height reduction of resist materials, such as a smaller height reduction 730 resulting from a 100% exposure level and a larger height reduction 732 resulting from a 60% exposure level. Resist patterning can be performed on the structure in FIG. 7C to form SROs on pads of substrate 102.

In another embodiment, the resist layer shown in FIG. 7C can be formed using maskless laser lithography techniques without mask 700, where the resist pattern is exposed directly onto top surface 105 using a spatial light modulator. In another embodiment, positive tone photoresist can be used for forming resist layers with variable thickness. In one embodiment, the pad density adjustment and exposure level adjustment can both be applied to achieve the determined resist thickness. For example, the resist layers described herein can be formed with imitation pads on surfaces of substrates, and the resist layers formed with imitation pads can be patterned using a mask with variable exposure levels. Positive tone photoresist or negative tone photoresist can be used for forming resist layers with variable thickness on surfaces with uniform pad density and surfaces with variable pad densities.

FIG. 8 illustrates a flow diagram relating to an implementation of optimized solder volume for flip-chip bonding in one embodiment. The process 800 in FIG. 8 may be implemented to form, for example, resist layers with variable thicknesses as discussed above. The process 800 can include one or more operations, actions, or functions as illustrated by one or more of blocks 802 and/or 804. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in different order, or performed in parallel, depending on the desired implementation.