Each channel structure 120 may include a channel layer 125 which provides a channel region of a memory cell string. The channel layer 125 may be formed of a semiconductor material such as silicon or germanium. The channel layer 125 may be formed in a tubular shape. The channel structure 120 may further include a capping layer 129 disposed in a central region of the tubular channel layer 125. The capping layer 129 may be disposed on a core insulating layer 127 disposed at a portion of the central region of the tubular channel layer 125, and be surrounded by an end portion of the channel layer 125. The capping layer 129 may be formed of a doped semiconductor layer. The doped semiconductor layer of the capping layer 129 may include at least one of an n-type impurity and a p-type impurity. In an embodiment, the doped semiconductor layer of the capping layer 129 may include an n-type impurity as a majority carrier. The channel layer 125 may extend to surround a sidewall of the capping layer 129 and a sidewall of the core insulating layer 127, and the end portion of the channel layer 125, which is adjacent to the capping layer 129, may be doped with the same impurity as the capping layer 129.

The memory layer 123 may be interposed between each of the plurality of conductive layers 115 and the channel structure 120. In an embodiment, the memory layer 123 may extend along a sidewall of the channel structure 120. Each channel structure 120 and a memory layer 123 corresponding thereto may form a cell plug. Each cell plug may correspond to a memory cell string.

The memory cell array 10 may be connected to a plurality of bit lines BL through a plurality of conductive contact structures 161. The plurality of conductive contact structures 161 may be formed of a conductive material, and respectively correspond to the plurality of channel structures 120.

The plurality of bit lines BL may be disposed above the gate stack structure GST. More specifically, the plurality of bit lines BL may be spaced apart from the gate stack structure GST. FIG. 4 illustrates an exploded perspective view with respect to the plurality of bit lines BL. The plurality of bit lines BL may be arranged to be in contact with the plurality of conductive contact structures 161 as shown in FIG. 6, and be respectively connected to the plurality of channel structures 120 via the plurality of conductive contact structures 161 as shown in FIG. 6.

The plurality of bit lines BL may extend in a direction intersecting major axes of the plurality of channel structures 120, and be arranged to be spaced apart from each other in a direction in which the major axes of the plurality of channel structures 120 face. In an embodiment, the major axes of the plurality of channel structures 120 may face in the first direction DR1, and minor axes of the plurality of channel structures 120 may face in the second direction DR2. The plurality of bit lines BL may be arranged to be spaced apart from each other in the first direction DR1, and extend in the second direction DR2.

The positions of the plurality of conductive contact structures 161 may be controlled such that each channel structure 120 is controlled by a bit line corresponding thereto among the plurality of bit lines and is independent from an operation of the other bit lines. For example, although two or more bit lines BL overlap with the one channel structure 120 on the one channel structure 120, the alignment position of a conductive contact structure 161 corresponding to the one channel structure 120 may be controlled on the one channel structure such that the conductive contact structure 161 is connected to one of the two or more bit lines BL. As described above, when the plurality of bit lines BL are disposed to be spaced apart from each other in the direction in which the major axis of the channel structure faces, an alignment margin of the conductive contact structure 161 for connecting the channel structure 120 to a bit line BL corresponding thereto may be secured even when two or more bit lines BL overlaps with one channel structure 120 on the one channel structure 120.

At least one conductive layer adjacent to the plurality of bit lines BL among the plurality of conductive layers 115 may be provided as the drain select line DSL1 or DSL2, and the others among the plurality of conductive layers 115 may be provided as the source select line SSL and the plurality of word lines WL1 to WLn. Intermediate conductive layers between the conductive layer provided as the drain select line DSL1 or DSL2 and the conductive layer provided as the source select line SSL may be used as the plurality of word lines WL1 to WLn.

FIG. 5A is a plan view an arrangement of a gate stack structure, a plurality of cell plugs, a plurality of conductive contact structures, and a plurality of bit lines of a semiconductor memory device in accordance with an embodiment of the present disclosure.

Referring to FIG. 5A, a gate stack structure GST may include a source select line SSL, a first drain select line DSL1, a second drain select line DSL2, and a plurality of word lines WL1 to WLn. A conductive layer for each of the source select line SSL, the first drain select line DSL1, the second drain select line DSL2, and the plurality of word lines WL1 to WLn may extend in the first direction DR1 and the second direction DR2 as described with reference to FIG. 4. As shown in FIG. 4, the plurality of word lines WL1 to WLn may be spaced apart from the source select line SSL in the third direction DR3. As shown in FIG. 4, the first drain select line DSL1 and the second drain select line DSL2 may be spaced apart from the plurality of word lines WL1 to WLn in the third direction DR3. The first drain select line DSL1, and the second drain select line DSL2 may be isolated from each other by an insulating structure 155 on the same plane (e.g., an XY plane). The first drain select line DSL1, and the second drain select line DSL2 may be spaced apart from each other in the second direction DR2 as an extending direction of a plurality of bit lines BL by the insulating structure 155.

A plurality of cell plugs CPL may be disposed inside the gate stack structure GST. The plurality of cell plugs CPL may extend in the third direction DR3 to penetrate the source select line SSL, the plurality of word lines WL1 to WLn, the first drain select line DSL1, and the second drain select line DSL2. The plurality of cell plugs CPL may be divided into a first cell plug group penetrating the first drain select line DSL1 and a second cell plug group penetrating the second drain select line DSL2. Each of the source select line SSL and the plurality of word lines WL1 to WLn may continuously extend in the second direction DR2 to surround cell plugs CPL of the first cell plug group and cell plugs CPL of the second cell plug group. Accordingly, each of the source select line SSL and the plurality of word lines WL1 to WLn may include a first memory cell array region overlapping with the first drain select line DSL1, a second memory cell array region overlapping with the second drain select line DSL2, and a connection region overlapping the insulating structure 155. The first memory cell array region and the second memory cell region of each of the source select line SSL and the plurality of word lines WL1 to WLn may be connected to each other by the connection region.

Each cell plug CPL may include a channel structure 120 inside the gate stack structure GST and a memory layer 123 between the channel structure 120 and the gate stack structure GST as described with reference to FIG. 4. A plurality of channel structures 120 of each of the first cell plug group and the second cell plug group may be regularly arranged in the first direction DR1 and the second direction DR2. In an embodiment, the plurality of channel structures 120 may be arranged in a zigzag pattern to increase an arrangement density.

FIG. 5B is an enlarged view of a cell plug shown in FIG. 5A.

Referring to FIGS. 5A and 5B, each cell plug CPL may have a cross-sectional structure including a major axis A1 facing in the first direction DR1 as an arrangement direction of the plurality of bit lines BL and a minor axis A2 facing in the second direction DR2 as an extending direction of the plurality of bit lines BL.

The channel structure 120 of the cell plug CPL may also have a cross-sectional structure including a major axis facing in the first direction DR1 and a minor axis facing in the second direction DR2, corresponding to the cross-sectional structure of the cell plug CPL. In an embodiment, a cross-sectional surface of the channel structure 120 may have substantially an elliptical shape. The channel structure 120 may include a channel layer 125 and a capping layer 129 as described with reference to FIG. 4.

The memory layer 123 may include a tunnel insulating layer TI, a data storage layer DS, and a blocking insulating layer BI. The tunnel insulating layer TI may extend to surround a sidewall of the channel structure 120. The data storage layer DS may extend to surround a sidewall of the tunnel insulating layer TI. The blocking insulating layer BI may extend to surround a sidewall of the data storage layer DS. The data storage layer DS may be formed of a material layer capable of storing data changed using Fowler-Nordheim tunneling. In an embodiment, the data storage layer DS may be formed of a nitride layer in which charges can be trapped. However, the embodiment of the present disclosure is not limited thereto, and the data storage layer DS may include a nano dot, a variable resistance layer, and the like. The blocking insulating layer BI may include oxide capable of blocking charges, and the tunnel insulating layer TI may include silicon oxide through which charges can tunnel.

The plurality of bit lines BL may be arranged to be spaced apart from each other in the first direction DR1, and be spaced apart from the plurality of channel structures 120 in the third direction DR3. Two or more bit lines BL may overlap with each channel structure 120. In accordance with the embodiment of the present disclosure, because a major axis of each channel structure 120 faces in the arrangement direction of the bit lines BL, the arrangement distance between the bit lines BL overlapping with the channel structure 120 and the width of each bit line BL may be widely secured even when the number of bit lines BL overlapping with the channel structure 120 is increased. In an embodiment, when the number of rows of channel structures 120 controlled by the drain select line DSL1 or DSL2 is increased, the number of insulating structures 155 for partitioning the drain select lines may be decreased, and thus the planar area allocated to the insulating structure 155 may be reduced.

Because of characteristics of an etching process performed in the third direction DR3 in a process of manufacturing the semiconductor memory device, in an embodiment, a planar area for a margin of the etching process may be increased in proportion to a stacked number of the word lines WL1 to WLn. As described above, in accordance with the embodiments of the present disclosure, the degree of integration of memory cells may be improved even when the stacked number of the word lines WL1 to WLn is not increased. Thus, in an embodiment, the degree of integration of memory cells may be improved without increasing the planar area for the margin of the etching process.

A plurality of conductive contact structures 161 may be disposed between the plurality of bit lines BL and the plurality of channel structures 120. The plurality of conductive contact structures 161 may correspond to the plurality of channel structures 120. Each conductive contact structure 161 may connect a channel structure 120 corresponding thereto to one of two or more bit lines BL overlapping the channel structure 120. To this end, the positions of the plurality of conductive contact structure 161 may be variously controlled according to an arrangement of the plurality of channel structures 120 and an arrangement of the plurality of bit lines BL.

Referring to FIG. 5A, the plurality of channel structures 120 of each of the first cell plug group and the second cell plug group may include a first channel structure 120[1], a second channel structure 120[2], and a third channel structure 120[3]. The first channel structure 120[1], the second channel structure 120[2], and the third channel structure 120[3] may be arranged in a line along the second direction DR2. The plurality of bit lines BL may include a first bit line BL[A], a second bit line BL[B], and a third bit line BL[C], which extend in the second direction DR2 to overlap with each of the first to third channel structures 120[1] to 120[3]. The first bit line BL[A], the second bit line BL[B], and the third bit line BL[C] may be spaced apart from each other in the first direction DR1. Central points CNP of the respective first to third channel structures 120[1] to 120[3] may be aligned in a line along the first bit line BL[A]. The first bit line BL[A] may be arranged between the second bit line BL[B] and the third bit line BL[C].

The plurality of conductive contact structure 161 may include a first conductive contact structure 161[1] between the first channel structure 120[1] and the third bit line BL[C], a second conductive contact structure 161[2] between the second channel structure 120[2] and the first bit line BL[A], and a third conductive contact structure 161[3] between the third channel structure 120[3] and the second bit line BL[B]. The first to third conductive contact structures 161[1] to 161[3] may be aligned at positions spaced apart from each other in the first direction DR1 and the second direction DR2 such that different bit lines can be connected to the first to third channel structures 120[1] to 120[3]. More specifically, the first conductive contact structure 161[1] may overlap with the first channel structure 120[1] at a position biased in a direction opposite to the first direction DR1 with respect to the central point CNP of the first channel structure 120[1]. The second conductive contact structure 161[2] may overlap with the central point CNP of the second channel structure 120[2]. The third conductive contact structure 161[3] may overlap with the third channel structure 120[3] at a position biased in the first direction DR1 with respect to the central point CNP of the third channel structure 120[3]. In accordance with the embodiment of the present disclosure, because the main axis of each channel structure 120 faces in the arrangement direction of the bit lines BL, an alignment margin of the conductive contact structure 161 may be secured even when the conductive contact structure 161 is disposed being biased to one side in the arrangement direction of the bit lines BL with respect to the central point CNP of the channel structure 120.

FIG. 6 illustrates a section of the semiconductor memory device taken along line I-I′ shown in FIG. 5A.

Referring to FIGS. 5A and 6, the gate stack structure GST may include a plurality of conductive layers 115 for the source select line SSL, the plurality of word lines WL1 to WLn, the first drain select line DSL1, and the second drain select line DSL2. Also, the gate stack structure GST may further include interlayer insulating layers 111 alternately disposed with the plurality of conductive layers 115 in the third direction DR3. The gate stack structure GST may include a plurality of channel holes 121 penetrating the plurality of conductive layers 115 and the plurality of interlayer insulating layers 111.

The memory layer 123 may extend along a sidewall of a channel hole 121 corresponding thereto. The channel layer 125 of the channel structure 120 may extend along an inner wall of the memory layer 123 in the channel hole 121. A central region of the channel hole 121, which is opened by the channel layer 125 of the channel structure 120, may be filled with a core insulating layer 127 and a capping layer 129.

The plurality of bit lines BL may be formed in an upper insulating layer 165 over the gate stack structure GST. An interposition insulating layer 151 may be disposed between the upper insulating layer 165 and the gate stack structure GST.

The interposition insulating layer 151 may be disposed on the gate stack structure GST, and extend to cover the plurality of channel structures 120. The interposition insulating layer 151 may be penetrated by the plurality of conductive contact structures 161. The interposition insulating layer 151 may insulate some of the plurality of channel structures 120 from some of the plurality of bit lines BL, and each conductive contact structure 161 may connect a bit line BL corresponding thereto and a channel structure 120 corresponding thereto to each other. In an embodiment, the first bit line BL[A] among the first to third bit lines BL[A] to BL[C] may be connected to the second channel structure 120[2] by the second conductive contact structure 161[2], and the second bit line BL[B] and the third bit line BL[C] may be insulated from the second channel structure 120[2] by the interposition insulating layer 151.

FIGS. 7A, 7B, and 7C are sectional views illustrating a connection structure between a doped semiconductor structure and a channel structure in accordance with embodiments of the present disclosure. Hereinafter, overlapping descriptions of components identical to the components shown in FIGS. 5A and 6 will be omitted.

Referring to FIGS. 7A to 7C, a semiconductor memory device may include a gate stack structure GST of a plurality of interlayer insulating layers 111 and a plurality of conductive layers 115, a core insulating layer 127 and a channel structure 120 inside the gate stack structure GST, a conductive contact structure 161 inside an interposition insulating layer 151, a bit line BL inside an upper insulating layer 165, and a doped semiconductor structure DPS.

The doped semiconductor structure DPS may include at least one doped semiconductor layer including at least one of an n-type impurity and a p-type impurity. In an embodiment, the doped semiconductor structure DPS may include, as a majority carrier, an impurity of the same conductivity as a capping layer 129 of the channel structure 120. In another embodiment, the doped semiconductor structure DPS may include a region having an n-type impurity as a majority carrier and a region having a p-type impurity as a majority carrier.

The doped semiconductor structure DPS may be in contact with a channel layer 125 of the channel structure 120, and be spaced apart from the capping layer 129 of the channel structure 120 with the core insulating layer 127 interposed therebetween. The connection structure between the doped semiconductor structure DPS and the channel structure 120 may be various.

Referring to FIG. 7A, the doped semiconductor structure DPS may include two or more semiconductor layers. In an embodiment, the doped semiconductor structure DPS may include a first semiconductor layer 101, a second semiconductor layer 103 on the first semiconductor layer 101, and a third semiconductor layer 105 on the second semiconductor layer 103.

The channel layer 125 may penetrate the third semiconductor layer 105, and extend to the inside of the first semiconductor layer 101. The second semiconductor layer 103 may be in contact with a portion of a sidewall of the channel layer 125, and extend between the first semiconductor layer 101 and the third semiconductor layer 105.

A memory layer 123 may be isolated into a first memory pattern 123A and a second memory pattern 123B by the second semiconductor layer 103. The first memory pattern 123A may extend between the channel layer 125 and the third semiconductor layer 105 and between the channel layer 125 and the gate stack structure GST. The second memory pattern 123B may be interposed between the channel layer 125 and the first semiconductor layer 101.

Referring to FIG. 7B, the doped semiconductor structure DPS may include a single semiconductor layer 107. The semiconductor layer 107 may be a single crystalline semiconductor layer or a multi-crystalline semiconductor layer.

The channel layer 125 may be in contact with the doped semiconductor structure DPS while penetrating the memory layer 123. The channel layer 125 may extend between the doped semiconductor structure DPS and the core insulating layer 127, and include a closed end portion facing the doped semiconductor structure DPS. The channel layer 125 may include a bottom surface in contact with the doped semiconductor structure DPS.