224, the second source/drain 252, and the second connection structure 235. A third thin film transistor T3 is formed by the third gate 233, the third semiconductor pattern 226, the third source/drain 253, and the fourth source/drain 254. In this embodiment, the first thin film transistor T1 is a double gate thin film transistor, and the double gate structure increases the electric current by 30%˜50% compared with a top gate structure.

In this embodiment, the first semiconductor pattern 222 is electrically connected to the second semiconductor pattern 224 through the first connection structure 234, the transfer wire 214, and the second connection structure 235, thereby relieving the problem of IR drop after the electric current flows through the first semiconductor pattern 222 and the second semiconductor pattern 224. Specifically, the resistivity of the semiconductor material (the first semiconductor pattern 222 and the second semiconductor pattern 224) is higher than the resistivity of the metal material (the first connection structure 234, the transfer wire 214, and the second connection structure 235). Thus, in response to directly connecting the first semiconductor pattern 222 to the second semiconductor pattern 224 by directly extending the first semiconductor pattern 222 or the second semiconductor pattern 224, the problem of IR drop occurs easily due to the high resistivity. In some embodiments, the transfer wire 214 has a sheet resistance of 0.1 Ω/μm²to 50 Ω/μm². In some embodiments, in response to both the first thin film transistor T1 and the second thin film transistor T2 being powered on, the electric current from the first source/drain 251 to the second source/drain 252 is greater than 1 μA (e.g., no less than 10 μA), and the IR drop from the first source/drain 251 to the second source/drain 252 is less than 0.1 volt.

In addition, the amount of insulating layer between the transfer wire 214 and the data line 255 is greater than the amount of insulating layer between the first semiconductor pattern 222 (or the second semiconductor pattern 224) and the data line 255. Thus, by electrically connecting the first semiconductor pattern 222 to the second semiconductor pattern 224 through the first connection structure 234, the transfer wire 214, and the second connection structure 235, the distance between the conductive path from the first semiconductor pattern 222 to the second semiconductor pattern 224 and the data line 255 is increased, thereby relieving the problem of parasitic capacitance.

In addition, designing the transfer wire 214 in the first conductive layer 210 effectively utilizes the circuit layout space, thereby facilitating the design of a high-resolution pixel circuit.

The fifth insulating layer 150 is located above the fourth insulating layer 140 and the fourth conductive layer 250, and the fourth conductive layer 250 is located between the fourth insulating layer 140 and the fifth insulating layer 150.

The fifth conductive layer 260 is located above the fifth insulating layer 150 and includes a first conductive structure 262 and a second conductive structure 264. The fifth conductive layer 260 includes a single-layer or multi-layer structure, and the material of the fifth conductive layer 260 includes, for example, chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, alloy or stacked layers of the above metals, or other metal materials. In some embodiments, the method for forming the fifth conductive layer 260 includes: depositing a fifth conductive material layer entirely on the fifth insulating layer 150, and then patterning the aforementioned fifth conductive material layer through a photolithographic process and an etching process, thereby forming the fifth conductive layer 260.

In this embodiment, before forming the fifth conductive layer 260, an opening O7 is formed through an etching process. The fifth conductive layer 260 is filled into the opening O7. Specifically, the opening O7 runs through the fifth insulating layer 150. The opening O7 overlaps the second source/drain 252.

The second conductive structure 264 is filled into the opening O7 to electrically connect to the second source/drain 252.

The sixth insulating layer 160 is located above the fifth insulating layer 150 and the fifth conductive layer 260, and the fifth conductive layer 260 is located between the fifth insulating layer 150 and the sixth insulating layer 160.

The sixth conductive layer 270 is located above the sixth insulating layer 160 and includes a first pad 272 and a second pad 274. The sixth conductive layer 270 includes a single-layer or multi-layer structure, and the material of the sixth conductive layer 270 includes, for example, metal oxides (e.g., indium tin oxide, indium zinc oxide, fluorine-doped indium oxide), metal nitrides (e.g., titanium nitride or molybdenum nitride), or a combination of the above materials. In some embodiments, the method for forming the sixth conductive layer 270 includes: depositing a sixth conductive material layer entirely on the sixth insulating layer 160, and then patterning the aforementioned sixth conductive material layer through a photolithographic process and an etching process, thereby forming the sixth conductive layer 270.

In this embodiment, before forming the sixth conductive layer 270, an opening O8 and an opening O9 are formed through an etching process. The sixth conductive layer 270 is filled into the opening O8 and the opening O9. Specifically, the opening O8 and the opening O9 run through the sixth insulating layer 160 The opening O8 and the opening O9 overlap the second conductive structure 264 and the first conductive structure 262 respectively.

The first pad 272 is filled into the opening O9 to electrically connect to the first conductive structure 262. The second pad 274 is filled into the opening O8 to electrically connect to the second conductive structure 264. The second pad 274 is electrically connected to the second source/drain 252 through the second conductive structure 264.

The light-emitting diode 300 is located above the sixth insulating layer 160 and bonded to the first pad 272 and the second pad 274. In this embodiment, the fifth insulating layer 150, the fifth conductive layer 260, the sixth insulating layer 160, and the sixth conductive layer 270 are included between the light-emitting diode 300 and the fourth conductive layer 250, but the disclosure is not limited thereto. In other embodiments, more insulating layers and conductive layers are included between the light-emitting diode 300 and the fourth conductive layer 250.

The light-emitting diode 300 includes a semiconductor stacking layer 320 and an electrode 310. The semiconductor stacking layer 320 includes stacking layers of N-type semiconductors and P-type semiconductors. In some embodiments, a light-emitting layer is further included between the N-type semiconductors and the P-type semiconductors. Two electrodes 310 are respectively formed on the N-type semiconductor and the P-type semiconductor.

In this embodiment, the electrodes 310 of the light-emitting diode 300 faces the first pad 272 and the second pad 274. In addition, the light-emitting diode 300 is connected to the first pad 272 and the second pad 274 by flip chip bonding through the conductive connection structure 280 (e.g., solder, conductive glue, or other conductive materials), but the disclosure is not limited thereto. In other embodiments, the electrodes 310 of the light-emitting diode 300 face away from the sixth insulating layer 160. In addition, after bonding the light-emitting diode 300 to the sixth insulating layer 160, another conductive connection structure is formed on the electrodes 310 to electrically connect the electrodes 310 to the first pad 272 and the second pad 274. In other embodiments, the electrodes 310 of the light-emitting diode 300 are respectively located on opposite sides of the semiconductor stacking layer 320. In addition, after connecting one of the electrodes 310 of the light-emitting diode 300 to one of the first pad 272 and the second pad 274, another conductive connection structure is formed on another electrode 310 to electrically connect another electrode 310 to the other of the first pad 272 and the second pad 274.

FIG. 2A is a schematic top view of an active device substrate 20 according to an embodiment of the disclosure. FIG. 2B is a cross-sectional schematic view along a line A-A′ of FIG. 2A. It must be noted here that the element reference numerals and a portion of the contents of the embodiments of FIG. 1A and FIG. 1B are used in the embodiment of FIG. 2A and FIG. 2B, the same or similar reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portion, reference may be made to the foregoing embodiment, and details are not described herein.

The difference between the active device substrate 20 in FIG. 2A and FIG. 2B and the active device substrate 10 in FIG. 1A and FIG. 1B is that: in the active device substrate 10, the first connection structure 234 and the second connection structure 235 belong to the second conductive layer 230. However, in the active device substrate 20, the first connection structure 244 and the second connection structure 246 belong to the third conductive layer 240.

Referring to FIG. 2A and FIG. 2B, the first conductive layer 210 is located between the substrate 100 and the first insulating layer 110 and includes a first bottom electrode 212 and a transfer wire 214. The second conductive layer 230 is located between the second insulating layer 120 and the third insulating layer 130 and includes a first gate 231, a second gate 232, a third gate 233, and a scanning line 236. The third conductive layer 240 is located between the third insulating layer 130 and the fourth insulating layer 140 and includes a capacitive electrode 242, a first connection structure 244, and a second connection structure 246. The fourth conductive layer 250 is located between the fourth insulating layer 140 and the fifth insulating layer 150 and includes a first source/drain 251, a second source/drain 252, a third source/drain 253, a fourth source/drain 254, a data line 255, and a working voltage line 256. The fifth conductive layer 260 is located between the fifth insulating layer 150 and the sixth insulating layer 160 and includes a first conductive structure 262 and a second conductive structure 264. The sixth conductive layer 270 is located on the sixth insulating layer 160 and includes a first pad 272 and a second pad 274.

In this embodiment, after forming the second conductive layer 230, the second conductive layer 230 is used as a mask to perform a doping process on the first semiconductor pattern 222, the second semiconductor pattern 224, and the third semiconductor pattern 226 to define the doped region and the passage region. The first passage region 222b of the first semiconductor pattern 222, the second passage region 224b of the second semiconductor pattern 224, and the third passage region of the third semiconductor pattern 226 are all overlapped on the second conductive layer 230. Since the second conductive layer 230 does not cover the first doped region 222c and the second doped region 224a, it is ensured that the portion of the first semiconductor pattern 222 contacting the first connection structure 244 and the portion of the second semiconductor pattern 224 contacting the second connection structure 246 are doped in the aforementioned doping process.

In this embodiment, before forming the third conductive layer 240, a first via H1 and a second via H2 are formed through an etching process. The third conductive layer 240 is filled in the first via H1 and the second via H2. Specifically, the first via H1 and the second via H2 run through the first insulating layer 110, the second insulating layer 120, and the third insulating layer 130. The first via H1 and the second via H2 overlap the transfer wire 214. The first connection structure 244 and the second connection structure 246 are respectively filled into the first via H1 and the second via H2 to electrically connect to the transfer wire 214.

In this embodiment, the part of the first via H1 above the first semiconductor pattern 222 and the part of the second via H2 above the second semiconductor pattern 224 have a first width W1, another part of the first via H1 below the first semiconductor pattern 222 and another part of the second via H2 below the second semiconductor pattern 224 have a second width W2. The first width W1 is greater than the second width W2.

By configuring the first via H1 and the second via H2 to overlap a part of the first semiconductor pattern 222 and a part of the second semiconductor pattern 224 respectively, the first connection structure 244 electrically connects the first semiconductor pattern 222 to the transfer wire 214 through a single first via H1, and the second connection structure 246 electrically connects the second semiconductor pattern 224 to the transfer wire 214 through a single second via H2. In this embodiment, the first connection structure 244 contacts a part of a top surface and a part of a side surface of the first semiconductor pattern 222, and the second connection structure