214. The second conductive layer 214 within the connector trench 510 may completely fill that trench, as shown, or just line that trench. The second conductive layer 214 is formed so as to be in electrical contact with the corresponding portion 218b of the M1 metallization layer; accordingly, the second conductive layer 214 can function as a second plate or electrode of the backside deep trench capacitor structure 502.

FIG. 6 is a cross-sectional diagram of an SOI IC 600 that includes a fifth example of a backside deep trench capacitor structure 602 in accordance with the present invention. The illustrated example is similar to the backside deep trench capacitor structure 402 of FIG. 4, but includes one or more additional intermediate conductive electrodes 604 and corresponding dielectric layers 606 formed within a capacitor trench 608 (one such pair of electrodes 604 and dielectric layers 606 are shown in FIG. 6). The additional intermediate conductive electrodes 604 enable stacks of positive and negative terminals for the capacitor backside deep trench capacitor structure 602 to further increase capacitive density. In the illustrated example, one intermediate conductive electrode 604 is electrically coupled to a corresponding portion 218b of the M1 metallization layer. Conductive electrodes 214 and 210, which “sandwich” intermediate conductive electrode 604, are shorted together and electrically coupled to a corresponding portion 218a of the M1 metallization layer. It should be appreciated that multiple stacked conductive electrodes may be formed in a similar manner, depending on the amount of capacitance density to be achieved.

Backside Deep Trench Inductor Structure Examples

The techniques described above may be used to create inductor structures as well. For example, FIG. 7A is a perspective diagram of an SOI IC 200 that includes a first example of a backside deep trench inductor structure 702 in accordance with the present invention. FIG. 7B is a top plan view of FIG. 7A, showing some elements in a dashed-line phantom view.

In the illustrated example, a set of parallel offset conductive trenches 704a-704c and 706b-706c are formed so as to connect from the backside 216 of the substrate 102 to corresponding portions of the M1 metallization layer within the superstructure 110. Pairs of those portions of the M1 metallization layer are connected through extents 708a-708c of the M1 metallization layer. Similarly, backside conductive extents 710a-710c (shown in a contrasting shading) are formed on the backside of the substrate 102 to connect pairs of the conductive trenches 704a-704c and 706b-706c.

Accordingly, a continuous coil of conductive material—an inductor—is formed by the conductive trenches 704a-704c and 706b-706c, the M1 metallization layer extents 708a-708c, and the backside conductive extents 710a-710c. Note that a dielectric layer (not shown) may be used to separate the first conductive layer 210 from the active silicon of the substructure 104. For an IC having a thickness in the range of 20-100 μm or more, the resulting inductor should have a relatively high Q factor.

A single IC may include one or more backside deep trench capacitor structures and one or more backside deep trench inductor structures.

Fabrication Considerations

For all of the example embodiments described above, the trenches (including connector trenches) and TSVs may be formed in the original substrate 102, or through a thinned version of the original substrate 102. For example, the original substrate 102 may be about 700-800 μm thick (before any thinning). For a variety of reasons, including final IC height constraints and heat dissipation, it may be desirable to thin the original substrate 102 so that the combined height of the superstructure 110, substruction 104, and substrate 102 is about 100-200 μm in thickness. Thinning of the substrate 102 may be accomplished, for example, by means of mechanical grinding or chemical mechanical polishing (CMP).

The trenches (including connector trenches) may be fabricated in a number of ways. For example, FIG. 8A shows a sequence of steps for one embodiment of the MACE process. The MACE process involves wet chemical etching of semiconductors (mainly silicon) with the use of a metal catalyst. For example, a metal catalyst may be deposited on the surface of a silicon substrate 800 in the form of nanoparticles 802 (STEP 1). The silicon substrate 800 is then subjected to an etching solution that enables the deposited metal catalyst nanoparticles 802 to dissolve the silicon, forming pores or trenches 806 containing the nanoparticles 802 (STEP 2). The nanoparticles 802 may then be dissolved, leaving just the pores or trenches 806 (STEP 3). The pores or trenches 806 may then be processed as described above to form a backside deep trench capacitor structure 808, as described above (STEP 4). FIG. 8B is an enlarged version of the structure resulting from STEP 4 of FIG. 8A. The illustrated example shows a first conductive layer 210, followed by a dielectric 212, followed by a second conductive layer 214.

Alternative processes for fabricating the trenches (including connector trenches) may include deep trench etching, deep reactive-ion etching (e.g., Bosch etching, a high-aspect ratio plasma etching process), wet etching, and porousization followed by a tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH) vapor etch. In some cases, an etching step may require an etch stop layer at the end to prevent damage to a connection layer (e.g., an associated portion of M1).

TSVs may be fabricated in a number of ways. “Via-first” TSVs are fabricated before individual devices (transistors, capacitors, resistors, etc.) are patterned during FEOL processing. “Via-middle” TSVs are fabricated during FEOL processing after the individual devices are patterned but before BEOL processing. “Via-last” TSVs are fabricated as part of BEOL processing.

It may be advantageous to form backside deep trench capacitor and/or inductor structures after FEOL processing. Currently, most of the high-density integrated capacitor processes (MIM, MOM, MOS) take place at the fab before or right after FEOL processing. However, the processing steps for forming trenches (including connector trenches) may be performed at a later stage of processing, including during BEOL processing or outsourced semiconductor assembly and test (OSAT) processing, which often will save money, simplify process flow, and improve the overall efficiency of fabrication by not needing to form backside deep trenches in-line at a CMOS fab—thus, a CMOS fab does not need the capabilities required for backside deep trench formation. Post-FEOL processing may also save die area because FEOL space is not consumed by the novel backside deep trench capacitor and/or inductor structures.

Post-FEOL processing to form backside deep trench capacitor and/or inductor structures is also advantageous if the substrate 102 has been thinned. Thinned substrate wafers may be fragile. Typically, in a 2-dimensional IC process flow, a thinned substrate wafer is singulated (diced) and individual IC dies are mounted on a reel of tape. The tape may then be sent to OSAT processing where the IC dies are picked from the tape and then placed on and attached to another structure, such as an interposer or laminate.

For example, FIG. 9 is a cross-sectional diagram of an IC die 900 mounted on another structure 902, such as an interposer or laminate, and surrounded by fill material 904 (e.g., epoxy). While the illustration shows the IC die 900 as including a backside deep trench capacitor structure 906, the IC die 900 may include a backside deep trench inductor structure. Further, it should be understood that a typical post-FEOL processing sequence in accordance with the present invention would be: (1) pick-and-place an IC die 900 (not having a backside deep trench capacitor or inductor structure) on the other structure 902 (interposer, laminate, etc.) so as to provide a suitably strong (less fragile) unit to work with in subsequent processing steps, (2) optionally surround the IC die 900 with fill material 904, and (3) subject the IC die 900 to one of the backside deep trench capacitor and/or inductor structure processes described above. After such processing, the unit structure (IC die 900 and other structure 902) may be attached or connected to other circuit structures (e.g., a PCB).

FIG. 9 describes part of a typical 2-dimensional IC process flow. FIG. 10 is a cross-sectional diagram of a first IC die 1000 being mounted onto a second IC die 1002 as part of a typical 3-dimensional IC process flow. While the illustration shows the first IC die 1000 as including a backside deep trench capacitor structure 1004, the first IC die 1000 may include a backside deep trench inductor structure. Further, it should be understood that a typical post-FEOL processing sequence in accordance with the present invention would be: (1) pick-and-place a first IC die 1000 (not having a backside deep trench capacitor or inductor structure) on a second IC die 1002 so as to provide a suitably strong (less fragile) unit to work with in subsequent processing steps, and (2) subject the first IC die 1000 to one of the backside deep trench capacitor and/or inductor structure processes described above. After such processing, the unit structure (first IC die 1000 and second IC die 1002) may be further processed to result in 3-dimensional circuit units that may be attached or connected to other circuit structures (e.g., a circuit module or PCB). Note that the first IC die 1000 may be attached to the second IC die 1002 using die-to-die bonding, or using die-to-wafer bonding (i.e., the second IC die 1002 is part of an unsingulated wafer), or using wafer-to-wafer bonding (i.e., both the first IC die 1000 and the second IC die 1002 are each part of a corresponding unsingulated wafer, or, in the case of the first IC die 1000, the first IC die 1000 is part of a reconstituted wafer mounting multiple ICs).

Circuit Embodiments

Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. IC embodiments of the present invention may be encased in IC packages and/or in modules for case of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

As one example of further integration of embodiments of the present invention with other components, FIG. 11 is a top plan view of a multi-IC substrate 1100 that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile). In the illustrated example, the substrate 1100 includes multiple ICs 1102a-1102d having terminal pads 1104 which would be interconnected by conductive vias and/or traces on and/or within the substrate 1100 or on the opposite (back) surface of the substrate 1100 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1102a-1102d may embody, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 1102b may be one or more instances of an IC chip module having one or more backside deep trench capacitor and/or inductor structures.

The substrate 1100 may also include one or more passive devices 1106 embedded in, formed on, and/or affixed to the substrate 1100. While shown as generic rectangles, the passive devices 1106 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected by conductive traces on or in the substrate 1100 to other passive devices 1106 and/or the individual ICs 1102a-1102d. The front or back surface of the substrate 1100 may be used as a location for the formation of other structures.

System Aspects

Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G New Radio, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

Methods

Another aspect of the invention includes methods of making at least one backside deep trench capacitor or inductor structures in an integrated circuit.