230 formed in the base cavity 231, and a base link region 237 formed under the extrinsic base region 250 may be monocrystalline. In an embodiment, one or more portions of the intrinsic base region 230 may have a narrower bandgap than the intrinsic emitter region 261. In an embodiment, the bandgap of the one or more portions of the base intermediate region 234 may be adjusted by changes in the Ge mole fraction. In an embodiment, the base buffer region 232 and the base intermediate region 234 may have the same bandgap (e.g., same Ge mole fraction, X). In an embodiment, the Ge mole fraction, X, may vary between about 0.05 and about 0.3 though other larger or smaller values of X may be used. In an embodiment, the value of the Ge mole fraction may be constant throughout the intrinsic base region 230. In other embodiments, the base buffer region 232 may have a narrower bandgap than the base intermediate region 234. In still other embodiments, the bandgap of the intrinsic base region 230 may be continuously graded through both the base buffer region 232 and the base intermediate region 234. In these embodiments, the grading of the base material, e.g., Si_1-XGe_Xmay include forming base intermediate region 234 with a wider bandgap and continuously reducing to a narrower bandgap in the base buffer region 232. In an embodiment, the base buffer region 232 may have a thickness of between about 50 angstroms and 500 angstroms. In other embodiments, the base buffer region 232 may have a thickness between about 20 angstroms and about 2000 angstroms, though other thicknesses may be used. In an embodiment, the base intermediate region 234 may have a thickness of between about 20 angstroms and 200 angstroms. In other embodiments, the base intermediate region 234 may have a thickness between about 20 angstroms and about 2000 angstroms, though other thicknesses may be used. In an embodiment, the base cap region 235 may have a thickness of between about 50 angstroms and 200 angstroms. In other embodiments, the base cap region 235 may have a thickness between about 20 angstroms and about 2000 angstroms, though other thicknesses may be used. In an embodiment of a p-type base region, the base intermediate region 234 may be doped with one or more of C, B, O, or In though other dopant species may be used. In an embodiment of a n-type base region (e.g., a pnp transistor device), the base intermediate region 234 may be doped with one or more of P, Li, As, Sb though other dopant species may be used. In an embodiment, the base buffer region 232 may be undoped. In other embodiments, the base buffer region 232 may be doped with a low-doping concentration (e.g., between around 1e16 cm⁻³and about 1e18 cm⁻³, although other higher or lower dopant concentrations may be used) and be doped as the same type as the collector region 220. In an embodiment, the doping concentration of the base intermediate region 234 may be in a range of about 5e17 cm⁻³to 1e20 cm⁻³. In other embodiments, the doping concentration of the base intermediate region 234 may be in a range of about 1e17 cm⁻³to 1e21 cm⁻³, though other higher or lower doping concentrations may be used. In an embodiment, the base cap region 235 may be undoped. In other embodiments, the base cap region 235 may be doped with the same type of dopant (i.e., n-type or p-type) as the base intermediate region 234 and may have a dopant concentration in a range of around 1e17 cm⁻³to around 1e18 cm⁻³, although higher or lower dopant concentrations may be used.

In an embodiment, the extrinsic base region 250 may be formed over the semiconductor substrate 210 and may be coupled to the intrinsic base region 230 through a base link region 237 formed in the base cavity 231. In an embodiment, the extrinsic base region 250 may include monocrystalline silicon. In some embodiments, the extrinsic base region 250 may include silicon-germanium. In further embodiments, the extrinsic base region 250 may include alternating silicon and silicon germanium layers. The alternating silicon and germanium layers may form a superlattice structure, according to an embodiment. In embodiments that include a p-type intrinsic base region 230 (e.g., a npn transistor device), the extrinsic base region may be doped with one or more of p-type dopant(s) B, O, In or Al, though other dopant species may be used. In embodiments that include a n-type intrinsic base region 230 (e.g., a pnp transistor device), the extrinsic base region 250 may be doped with one or more of n-type dopant(s) such P, Li, As, or Sb, though other dopant species may be used. In an embodiment, the extrinsic base region 250 may include the same dopant species as the intrinsic base region 230. For example, the intrinsic base region 230 and the extrinsic base region 250 may both include B doping.

In an embodiment, the extrinsic base region 250 may include a monocrystalline region 254 formed over base link region 237 within the base cavity 231 and a polycrystalline region 256 formed in areas of the device adjacent the monocrystalline region 254, over the dielectric region 214. In an embodiment, a base electrode 259 may be coupled to extrinsic base region 250 in the polycrystalline region 256 through a base contact layer 258.

In an embodiment, a thickness of the extrinsic base region 250 may be between about 100 angstroms and 1500 angstroms although other thicknesses may be used. In an embodiment, the hole mobility of the extrinsic base region 250 in the monocrystalline region 254 may between about 100 cm²/V-s and about 200 cm²/V-s while the associated sheet resistance, R_sh, of the extrinsic base region 250 in the monocrystalline region 254 may be between about 30 ohms per square and about 60 ohms per square. In other embodiments, the mobility of the extrinsic base region 250 in the monocrystalline region 254 may between about 50 cm²/V-s and about 300 cm²/V-s, while the associated R_shof the extrinsic base region may be between about 20 ohms per square and about 120 ohms per square. The hole mobility of the extrinsic base region 250 in the polycrystalline region 256 may between about 30 cm²/V-s and about 60 cm²/V-s while the associated sheet resistance, R_sh, of the extrinsic base region 250 in the monocrystalline region 254 may be between about 200 ohms per square and about 900 ohms per square. In other embodiments, the mobility of the extrinsic base region 250 in the polycrystalline region 256 may between about 10 cm²/V-s and about 100 cm²/V-s, while the associated R_shof the extrinsic base region may be between about 80 ohms per square and about 1000 ohms per square.

In an embodiment, the emitter region 260 may be formed over the intrinsic base region 230. According to an embodiment, the emitter region 260 may include an intrinsic emitter region 261, a first emitter spacer layer 263, a second emitter spacer layer 264, extrinsic emitter region 265, and an emitter contact layer 268 formed over the intrinsic emitter region 261. The emitter region 260 may also include an emitter electrode 269 formed over the emitter contact layer 268, according to an embodiment.

In an embodiment, the intrinsic emitter region 261 may be formed over the intrinsic base region 230, the second emitter spacer layer 264, the first emitter spacer layer 263. In an embodiment, the intrinsic emitter region 261 may be formed using a monocrystalline n-type semiconductor. In other embodiments, the intrinsic emitter region 261 may be formed using a p-type semiconductor. In an embodiment, the intrinsic emitter region 261 may have a thickness of between about 100 angstroms and 1000 angstroms. In other embodiments, the intrinsic emitter region 261 may have a thickness of between about 50 angstroms and about 5000 angstroms, though other thicknesses may be used. In an embodiment that includes a p-type emitter region 260 (e.g., a pnp transistor device), the intrinsic emitter region 261 may be monocrystalline and be doped with one or more of B, O, Al, or In though other dopant species may be used. In an embodiment of an n-type emitter region (e.g., a npn transistor device), the intrinsic emitter region 261 may be doped with one or more of P, Li, As, or Sb though other dopant species may be used. In an embodiment, the doping concentration of the intrinsic emitter region 261 may be in a range of about 5e17 cm⁻³to 5e21 cm⁻³.

The extrinsic emitter region 265 may be coupled to the intrinsic emitter region 261, the second emitter spacer layer 264, the first emitter spacer layer 263, and emitter dielectric stack 262. In an embodiment, the extrinsic emitter region 265 may be formed using a polycrystalline n-type semiconductor. In other embodiments, the extrinsic emitter region 265 may be formed using a p-type semiconductor. In an embodiment, the extrinsic emitter region 265 may have a thickness of between about 100 angstroms and 1000 angstroms. In other embodiments, the extrinsic emitter region 265 may have a thickness of between about 50 angstroms and about 5000 angstroms, though other thicknesses may be used. In an embodiment that includes a p-type emitter region 260 (e.g., a pnp transistor device), the extrinsic emitter region 265 may be polycrystalline and be doped with one or more of B, O, Al, or In though other dopant species may be used. In an embodiment of an n-type emitter region (e.g., a npn transistor device), the extrinsic emitter region 265 may be doped with one or more of P, Li, As, or Sb though other dopant species may be used. In an embodiment, the doping concentration of the extrinsic emitter region 265 may be in a range of about 5e17 cm-3 to 5e21 cm-3.

According to an embodiment, the emitter contact layer 268 may be formed over the intrinsic emitter region 261. In an embodiment, the emitter contact layer 268 may be formed using titanium-tungsten (TiW), titanium tungsten nitride (TiWN), tungsten silicide (WSi), cobalt silicide (CoSi), platinum silicide (PtSi), nickel platinum silicide (NiPtSi), or other suitable material(s). The emitter electrode 269 may be formed over the emitter contact layer 268, according to an embodiment. In an embodiment, the emitter electrode 269 may be formed from one of copper, aluminum, tungsten, or other suitable conducting materials.

FIG. 3 depicts a further embodiments of bipolar transistor devices with extrinsic bases having monocrystalline regions. FIG. 3 is a cross sectional side view of an exemplary bipolar transistor device 300, according to an embodiment. In this embodiment a first extrinsic portion 366 of the extrinsic portion of the emitter region 360 is monocrystalline The numbered drawings in FIG. 3 have like numbering and may be compared to the description and reference numbers associated with FIG. 2. For example, the semiconductor substrate 210 in FIG. 2 correspond to the semiconductor substrate 310 in FIG. 3. Also, for the sake of brevity, descriptions of numbered references and fabrication details associated with each numbered item may not be repeated where adequate descriptions were given in connection with the descriptions of FIG. 2.

The bipolar transistor device 300 may include a semiconductor substrate 310 that includes semiconductor regions to define a collector region 320, an intrinsic base region 330, an extrinsic base region 350, and an emitter region 360, as described above. A number of other components of the bipolar transistor device 300 may be configured in a manner similar to the bipolar transistor device 200 of FIG. 2. For example, the semiconductor substrate 310 and its associated semiconductor regions (e.g., dielectric region 314, collector region 320, SIC 324, sub-collector 326, sub-contact region 327, collector contact layer 328, collector electrode 329, intrinsic base region 330, base cavity 331, base buffer region 332, base intermediate region 334, base cap layer 335, extrinsic base region 350, monocrystalline region 354, polycrystalline portion 356, base contact layer 358, base electrode 359, intrinsic emitter region 361, emitter dielectric layer stack 362, emitter contact layer 368, and emitter contact 369) may be formed in a similar manner as like-numbered components of bipolar transistor device 200 of FIG. 2.

Referring again to FIG. 3, an extrinsic emitter region 365 of the emitter region 360 may be formed over emitter spacer layers 363, 364. A first extrinsic portion 366 of the extrinsic emitter region 365 of the emitter region 360 may in include a monocrystalline material. A second portion 367 of the extrinsic portion may include a polycrystalline material.

FIGS. 4A, 4B, and 4C depict process flow diagrams alongside corresponding cross-sectional views detailing partial formation of an area 4 of FIG. 2, and describing a method 400 for fabricating the bipolar transistor device 200 of FIG. 2, in accordance with an embodiment. References to optional process steps to realize the bipolar transistor device 300 of FIG. 3 have been added, where appropriate. In an embodiment, the method 400 includes a sequence of steps, for which only the salient are shown for convenience in illustration. For example, the method 400 may include a number of acts directed to preparing the semiconductor substrate for the fabrication method that are not described in detail herein. The ordering of the acts may vary in other embodiments.

Referring to FIG. 4A, in block 402, an embodiment of the method 400 may include forming a collector region 220 within a semiconductor substrate 210, forming a sub-collector region 226, forming a dielectric region 214 adjacent the collector region 220, forming extrinsic base region 250, and forming emitter dielectric stack 262, according to an embodiment. In an embodiment, forming the sub-collector region 226 may include implanting a dopant species (e.g., phosphorus) using ion implantation (not shown). Forming the collector region 220 may include using dry or wet etching to form a collector mesa defined by collector sidewall 225. In an embodiment, a dielectric material (e.g., SiO₂or TEOS) may be deposited around the collector sidewall 225 and over the upper surface 221 of the collector to form a dielectric region 214 for, e.g., shallow trench isolation (STI) to provide isolation between adjacent devices. In an embodiment, the dielectric region 214 may be formed using plasma enhanced chemical vapor phase deposition (PECVD), low pressure chemical vapor phase deposition (LPCVD), chemical vapor phase deposition (CVD), thermal growth techniques, or other suitable deposition techniques.

Referring again to FIG. 4A, in block 402, the method may include forming a collector region 220 within a semiconductor substrate 210, forming dielectric region 214 over the collector region 220, forming extrinsic base region 250 over the collector region 220, and forming the emitter stack region over the extrinsic base region 250, according to an embodiment. In an embodiment, the collector region 220 may be formed by first, implanting the sub-collector region 226 by implanting a dopant species (e.g., arsenic) using ion implantation (not shown).

Forming the collector region 220 may be continued by using dry or wet etching to form a collector mesa. In an embodiment, a dielectric material (e.g., TEOS) may be deposited around the collector mesa defined by collector sidewall 225 to form the dielectric region 214 for, e.g., shallow trench isolation (STI) to provide isolation between adjacent devices.

In an embodiment, the extrinsic base region 250 may be formed using, e.g., polysilicon and may be grown using MOCVD, CVD, LPCVD, PECVD, or other suitable techniques. In an embodiment, the extrinsic base region 250 may be doped with a suitable dopant (e.g., B doping for a npn transistor). In an embodiment, the extrinsic base region may between about 500 angstroms thick and about 1000 angstroms thick, though other thicknesses may be used. In another embodiment, the extrinsic base region 250 may between about 100 angstroms thick and about 1500 angstroms thick, though other thicknesses may be used.

In an embodiment, forming the emitter dielectric stack 262 may include forming a first dielectric layer 262A (e.g., tetraethyl orthosilicate (TEOS)) over the collector region 220, forming a second dielectric layer 262B (e.g., silicon nitride (SiN)) over the first dielectric layer 262A, and forming a third dielectric layer 262C (e.g., TEOS) over the second dielectric layer 262B. Each of the first dielectric layer 262A, the second dielectric layer 262B, and the third dielectric layer 262C may include a portion disposed over the collector region 220, according to an embodiment. In an embodiment, each of the layers of the emitter dielectric stack 262 may be formed using plasma enhanced chemical vapor phase deposition (PECVD), low pressure chemical vapor phase deposition (LPCVD), chemical vapor phase deposition (CVD), thermal growth techniques, or other suitable deposition techniques. For example, LPCVD may be used to form SiN layers and PECVD may be used to form TEOS layers, according to an embodiment. In an embodiment, the first dielectric layer 262A (e.g., oxide) may between about 20 angstroms thick and about 200 angstroms thick, though other thicknesses may be used. In an embodiment, the second dielectric layer 262B (e.g., nitride) may between about 20 angstroms thick and about 200 angstroms thick, though other thicknesses may be used. In an embodiment, the third dielectric layer 262C (e.g., oxide) may between about 20 angstroms thick and about 200 angstroms thick, though other thicknesses may be used.

Referring now to FIG. 4A, block 404, an embodiment of the method 400 may include etching emitter dielectric stack 262 to form the emitter window 430. According to an embodiment of the method, the first, second, and third dielectric layers 262A, 262B, 262C may be etched using one or more wet and dry etches (not shown). In an embodiment, the wet etches may be accomplished using buffered oxide etch (a mixture of ammonium fluoride and hydrofluoric acid), hydrofluoric acid, or other suitable wet chemistries. The dry etches may be accomplished using sulfur hexafluoride, carbon tetrachloride, boron trichloride gases in a plasma etching system. Plasma etching may be accomplished using reactive ion etching (RIE), inductively coupled plasma (ICP) etching, or other suitable etch techniques. In an embodiment, wet etching may be used to remove oxide-based films (e.g., TEOS and other oxides) while nitride-based films (e.g., SiN and other nitrides) may be etched with F-based dry etching. In another embodiment, dry etching may be used to remove both the oxide and nitride films. In an embodiment, the extrinsic base region 250 may be etched using dry or wet chemistries (e.g., hydrobromic acid (HBr) and chlorine (Cl)-based etching). In an embodiment, the emitter window etch may stop on the dielectric region 214 over the collector region 220.

Referring to FIG. 4A, block 406, and in an embodiment, the first inside spacer layer 266 may be formed using, e.g., SiN and the dielectric deposition methods described above (e.g., PECVD, LPCVD, thermal deposition). In an embodiment, the first inside spacer may between about 50 angstroms and about 400 angstroms in thickness.

Referring to FIG. 4A, block 408, an embodiment of the method 400 may optionally include implanting collector region 220 to form the SIC region 224, according to an embodiment. According to an embodiment, implanting the collector region 220 may include ion implantation to incorporate a dopant species into the collector region 220. A SIC implant may be used to form the SIC region 224 In an embodiment, a dopant species 438 (e.g., phosphorous or arsenic) may be implanted to form the SIC region 224. In other embodiments (not shown), the SIC region 224 may be replaced with an epitaxially grown region, formed using epitaxial growth such as metal organic chemical vapor phase epitaxy (MOCVD), chemical vapor phase epitaxy (CVD), molecular beam epitaxy (MBE), or other suitable methods.

Referring to FIG. 4A, block 410, an embodiment of the method 400 may include etching base cavity 231, according to an embodiment. In an embodiment, forming base cavity 231 may include etching dielectric region 214, according to an embodiment. The base cavity 231 may be formed by wet etching the dielectric region 214 using isotropic wet and/or dry etching performed using one of the techniques described above. In an embodiment, the base cavity etch may expose an upper surface 221 of the collector region 220.

Referring to FIG. 4A, block 412, an embodiment of the method 400 may include forming intrinsic base region 230, according to an embodiment. In an embodiment, the base buffer region 232 may be formed using selective epitaxial growth over the exposed surface of collector region 220. In an embodiment, CVD or MOCVD may be used to epitaxially grow the base buffer region 232 using selective epitaxial growth. In an embodiment, the selective epitaxial growth may be facilitated by allowing the epitaxial material to only nucleate on the exposed semiconductor regions (e.g., the collector region