200. For example, the barrier structure 140 may include an overlapping region overlapping the second semiconductor chip 200 in the Z direction, and a non-overlapping region that does not overlap the second semiconductor chip in the Z direction. The non-overlapping region may extend in an outward direction, with respect to the fillet portion 240P of the adhesive layer 240. The barrier structure 140 may have an outer sidewall 140S 1 and an inner sidewall 140S2 in a plan view (refer to FIG. 1). The outer sidewall 140S1 may be disposed in an outward direction, with respect to the fillet portion 240P of the adhesive layer 240. The outer sidewall 140S1 may be disposed in an outward direction, with respect to a side surface of the semiconductor chip 200. The outer sidewall 140S1 may be disposed in an inward direction, with respect to a side surface of the first semiconductor chip 100. The inner sidewall 140S2 may overlap the second semiconductor chip 200.

The barrier structure 140 may be formed of a photosensitive material such as a photoimageable dielectric (PID) or photo-sensitive polyimide (PSPI). The barrier structure 140 may include a material having a lower modulus of elasticity than the adhesive layer 240.

The second semiconductor chip 200 may be disposed on the first semiconductor chip 100. The second semiconductor chip 200 may include a second semiconductor layer 201 and a second device layer 210. The second semiconductor chip 200 may be stacked in a face-to-face manner such that the second device layer 210 faces the first device layer 110 of the first semiconductor chip 100, but the present inventive concept is not necessarily limited thereto. A first surface 200S1, the lower surface of the semiconductor chip 200, may face the first surface 100S1 of the first semiconductor chip 100. Unlike the first semiconductor chip 100, the second semiconductor chip 200 might not include a through-via, but the present inventive concept is not necessarily limited thereto.

The second semiconductor layer 201 may include the same or similar material as the first semiconductor layer 101. The second semiconductor layer 201 may have a smaller size than the first semiconductor layer 101, but the present inventive concept is not necessarily limited thereto.

The second device layer 210 may include second integrated circuits disposed below a lower surface (e.g., the active surface) of the second semiconductor layer 201. The second integrated circuits may include memory devices that store and/or output data based on an address command, a control command, and the like received from the first semiconductor chip 100. For example, the memory devices may include volatile memory devices such as a DRAM and an SRAM, or non-volatile memory devices such as a PRAM, an MRAM, an FeRAM, or an RRAM. In this case, semiconductor packages, according to embodiments of the present inventive concept, may be used in a high bandwidth memory (HBM) product, an electro data processing (EDP) product, or the like.

The second device layer 210 may include a second interlayer insulating layer 211, a second interconnection structure 212, and second connection pads 214.

The second interlayer insulating layer 211 may include the same material as the first interlayer insulating layer 111. The second interlayer insulating layer 211 may include a plurality of layers.

The second interconnection structure 212 may have a multi-layered structure including a second interconnection layer and a second via. The second interconnection structure 212 may include, for example, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or titanium (Ti), a nitride of the metal material, or an alloy of the metal materials.

The second connection pads 214 may be disposed below the first surface 200S1 of the second semiconductor chip 200, and may be electrically connected to the second interconnection structure 212. The second connection pads 214 may include, for example, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or titanium (Ti), a nitride of the metal material, or an alloy of the metal materials.

The connection bumps 235 may be in contact with the first connection pads 114 and the second connection pads 214 between the first semiconductor chip 100 and the second semiconductor chip 200. The connection bumps 235 may include bumps for communication with an external device (e.g., ‘800’ in FIG. 9), in addition to bumps for communication between the first semiconductor chip 100 and the second semiconductor chip 200. The connection bumps 235 may include a low-melting-point metal, or, for example, an alloy including tin (Sn) (e.g., Sn—Ag—Cu) or another metal having a melting point that is the same as or lower than that of one or more of the forgoing. The connection bumps 235 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and/or an alloy thereof. The alloy may include, for example, Sn—Pb, Sn—Ag, Sn—Au, Sn—Cu, Sn—Bi, Sn—Zn, Sn—Ag—Cu, Sn—Ag—Bi, Sn—Ag—Zn, Sn—Cu—Bi, Sn—Cu—Zn, Sn—Bi—Zn, or the like. The connection bumps 235 may include, for example, a solder ball. Each of the connection bumps 235 may have a land shape, a ball shape, or a pin shape. Each of the connection bumps 235 may be formed as a multi-layer or a single layer.

The adhesive layer 240 may at least partially surround the connection bumps 235. The adhesive layer 240 may be a non-conductive (e.g., a dielectric) material layer that electrically insulates adjacent connection bumps 235 from each other. The non-conductive material may include an epoxy-based material that does not contain conductive particles, and the adhesive layer 240 may be, e.g., a non-conductive film (NCF). The adhesive layer 240 may include any type of polymer film that may be subjected to a thermocompression process. The adhesive layer 240 may include the fillet portion 240P flowing and protruding from the side surface of the second semiconductor chip 200 in an outward direction. The fillet portion 240P may extend in the X and Y directions from a portion in which the adhesive layer 240 is interposed between the first semiconductor chip 100 and the second semiconductor chip 200. The fillet portion 240P may be in contact with the side surface of the second semiconductor chip 200. The adhesive layer 240 may fix the first semiconductor chip 100 and the second semiconductor chip 200 to maintain a chip stack structure of the semiconductor package. The fillet portion 240P of the adhesive layer 240 may be in contact with the barrier structure 140. The adhesive layer 240 may be in contact with is the first device layer 110, the second device layer 210, and the barrier structure 140.

A semiconductor package 1000, according to an embodiment, may further include an encapsulant 250 at least partially surrounding the side surface of the second semiconductor chip 200 on the first semiconductor chip 100, and covering the fillet portion 240P of the adhesive layer 240, and the barrier structure 140. As illustrated in FIG. 2, the encapsulant 250 may expose the upper surface of the second semiconductor chip 200. In some embodiments, the encapsulant 250 may cover the upper surface of the second semiconductor chip 200. The encapsulant 250 may include, for example, an epoxy mold compound (EMC), but a material of the encapsulant 250 is not necessarily limited to this approach.

FIG. 4 is a schematic plan view of a semiconductor package according to an embodiment of the present inventive concept.

Referring to FIG. 4, a semiconductor package 1000A may be similar to the semiconductor package 1000 of FIGS. 1 to 3A, but a barrier structure 140a may have a dam shape completely surrounding a central region CR in which connection bumps 235 are arranged. For example, in a region below a corner 200C of a lower surface 200S1 of a second semiconductor chip 200, the barrier structure 140a might not be disconnected, but may extend continuously. Since the semiconductor package 1000A includes the barrier structure 140a, propagation of a crack CP from a void V formed in an adhesive layer 240 to a first device layer 110 of a first semiconductor chip 100 may be prevented, as described above with reference to FIG. 3A.

FIG. 5 is a schematic plan view of a semiconductor package according to an embodiment of the present inventive concept.

Referring to FIG. 5, a semiconductor package 1000B may be similar to the semiconductor package 1000A of FIG. 4, but a barrier structure 140b may have a shape in which a width decreases toward a corner 200C of a lower surface 200S1 of a second semiconductor chip 200. For example, the barrier structure 140b may include a barrier pattern including portions having different widths in one direction.

FIG. 6 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept.

Referring to FIG. 6, a semiconductor package 1000C may be similar to that of FIGS. 1 to 3A, but a barrier structure 140c may cover a plurality of first connection pads 114c, and may extend longer in the X direction, with respect to the other embodiments. Since the semiconductor package 1000C includes the barrier structure 140c, propagation of a crack CP from a void V formed in an adhesive layer 240 to a first device layer 110 of a first semiconductor chip 100 may be prevented, as described above with reference to FIG. 3A.

FIG. 7 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept.

Referring to FIG. 7, a semiconductor package 1000D may have the same or similar characteristics as those described with reference to FIGS. 1 to 3A, except that the semiconductor package 1000D further includes a package substrate 300 on which a first semiconductor chip 100 is mounted.

As an example, the first semiconductor chip 100 may be, for example, a logic chip including a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application specific integrated circuit (ASIC), or the like. In addition, a second semiconductor chip 200 may include a memory chip such as a DRAM, an SRAM, a PRAM, an MRAM, an FeRAM, or an RRAM. For example, the second semiconductor chip 200 may include a power management IC (PMIC) chip.

For example, the package substrate 300 may include a lower pad 312 disposed on a lower surface of a body, an upper pad 311 disposed on an upper surface of the body, and a redistribution circuit 313 for electrically connecting the lower pad 312 and the upper pad 311. The package substrate 300 may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape interconnection board, or the like. The body of the package substrate 300 may include a different material depending on a type of the substrate. For example, when the package substrate 300 is a printed circuit board, the body may be in a form in which a copper clad laminate is additionally stacked, or an interconnection layer is additionally stacked on one surface or both surfaces of the copper clad laminate. A solder resist layer may be respectively formed on lower and upper surfaces of the package substrate 300. The upper and lower pads 311 and 312 and the redistribution circuit 313 may form an electrical path connecting the lower surface and the upper surface of the package substrate 300. An external connection terminal 320 connected to the lower pad 312 may be disposed below the package substrate 300. The external connection terminal 320 may be formed of a conductive material having a shape such as a ball shape, a pin shape, or the like.

FIG. 8 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept.

Referring to FIG. 8, a semiconductor package 1000E may have the same or similar characteristics as those described with reference to FIGS. 1 to 3A, except that a second semiconductor chip on a first semiconductor chip 100 is provided as a plurality of second semiconductor chips 200A, 200B, 200C, and 200D. An encapsulant 250 may expose an upper surface of an uppermost second semiconductor chip 200D, but may also cover the upper surface of the uppermost second semiconductor chip 200D, according to an embodiment. The number of the plurality of second semiconductor chips 200A, 200B, 200C, and 200D is not necessarily limited to that illustrated in the drawings, and may be, for example, two, three, five, or more.

The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may be disposed on the first semiconductor chip 100. Among the plurality of second semiconductor chips 200A, 200B, 200C, and 200D, remaining semiconductor chips, except for the uppermost second semiconductor chip 200D, may further include a second through-via 220 and third connection pads 234. The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may be electrically connected to each other by connection bumps 235 disposed between second connection pads 214 and the third connection pads 234. According to embodiments, the connection bumps 235 may be omitted, and the second connection pad 214 and the third connection pad 234 may be in direct contact with and be bonded to each other. The second through-via 220 may have similar characteristics to a first through-via 120, and to the extent that a detailed description of an element has been omitted, it may be assumed that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

For example, the first semiconductor chip 100 may be a buffer chip including a plurality of logic devices and/or a plurality of memory devices. Therefore, signals from the plurality of second semiconductor chips 200A, 200B, 200C, and 200D stacked on the first semiconductor chip 100 may be transferred to an external source, and a signal and power from the external source may be transmitted to the plurality of second semiconductor chips 200A, 200B, 200C, and 200D. The semiconductor chip 100 may perform a logic function and a memory function together by the logic devices and the memory devices. According to an embodiment, the logic functions may be performed by including the logic devices. The plurality of second semiconductor chips 200A, 200B, 200C, and 200D may include, for example, volatile memory devices such as a DRAM and an SRAM, or non-volatile memory devices such as a PRAM, an MRAM, an FeRAM, or an RRAM. For example, the semiconductor package 1000E of the present embodiment may be used in a high bandwidth memory (HBM) product, an electro data processing (EDP) product, or the like.

FIG. 9 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present inventive concept.

Referring to FIG. 9, a semiconductor package 2000, according to an embodiment, may include a package substrate 600, an interposer substrate 700, and at least one chip structure 1000E (e.g., the semiconductor package of FIG. 8). Also, the semiconductor package 2000 may further include a logic chip and/or a processor chip 800 disposed adjacent to the chip structure 1000E and on the interposer substrate 700.

The package substrate 600 may include a lower pad 612 disposed on a lower surface of a body, an upper pad 611 disposed on an upper surface of the body, and a redistribution circuit 613 electrically connecting the lower pad 612 and the upper pad 611 to each other. The package substrate 600 may be a support substrate on which the interposer substrate 700, the logic chip 800, and the chip structure 1000E are mounted, and may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape interconnection board, or the like. The body of the package substrate 600 may include a different material depending on a type of the substrate. For example, when the package substrate 600 is a printed circuit board, the body may be in a form in which a copper clad laminate is additionally stacked, or an interconnection layer is additionally stacked on one surface or both surfaces of the copper clad laminate. A solder resist layer may be respectively formed on lower and upper surfaces of the package substrate 600. The lower and upper pads 612 and 611 and the redistribution circuit 613 may form an electrical path connecting the lower surface and the upper surface of the package substrate 600. The lower and upper pads 612 and 611 and the redistribution circuit 613 may be formed of a metal material, for example, copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), and/or zinc (Zn), and may also include carbon (C), or the lower and upper pads 612 and 611 may include an alloy comprising two or more of the above-listed materials. The redistribution circuit 613 may include multiple redistribution layers, and vias connecting the multiple redistribution layers. An external connection terminal 620 connected to the lower pad 612 may be disposed on a lower surface of the package substrate 600. The external connection terminal 620 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) and/or or an alloy thereof.

The interposer substrate 700 may include a substrate 701, a lower protective layer 703, a lower pad 705, an interconnection structure 710, a metal bump 720, and a through-via 730. The chip structure 1000E and the processor chip 800 may be stacked on the package substrate 600 via the interposer substrate 700. The interposer substrate 700 may electrically connect the chip structure 1000E and the processor chip 800 to each other.

The substrate 701 may be formed of, for example, an organic material, a plastic, and/or a glass substrate. When the substrate 701 is a silicon substrate, the interposer substrate 700 may be referred to as a silicon interposer. Also, when the substrate 701 is an organic substrate, the interposer substrate 700 may be referred to as a panel interposer.

The lower protective layer 703 may be disposed on a lower surface of the substrate 701, and the lower pad 705 may be disposed on the lower protective layer 703. The lower pad 705 may be connected to the through-via 730. The chip structure 1000E and the processor chip 800 may be electrically connected to the package substrate 600 through the metal bumps 720 disposed on the lower pad 705.

The interconnection structure 710 may be disposed on an upper surface of the substrate 701, and may include an interlayer insulating layer 711, and a single-layer or multi-layer interconnection structure 712. When the interconnection structure 710 has a multi-layered interconnection structure, interconnection patterns of different layers may be connected to each other through a contact via.

The through-via 730 may extend from the upper surface to the lower surface of the substrate 701, and may pass through the substrate 701. In addition, the through-via 730 may extend into the interconnection structure 710, and may be electrically connected to interconnections of the interconnection structure 710. When the substrate 701 is a silicon substrate, the through-via 730 may be referred to as a TSV. Other structures and materials of the through-via 730 may be the same as those described for the semiconductor package 1000 of FIG. 1. According to an embodiment, the interposer substrate 700 may include only an interconnection structure therein, but might not include a through-via.

The interposer substrate 700 may be used for the purpose of converting or transferring an input electrical signal between the package substrate 600 and the chip structure 1000E or the processor chip 800. Therefore, the interposer substrate