2003 that serves as a data storage space. The DRAM device 2004 included in the electronic system 2000 may operate as a kind of cache memory, and may provide a space for temporary data storage in a control operation of the semiconductor package 2003. When the DRAM device 2004 is included in the electronic system 2000, the controller 2002 may include not only a NAND controller for controlling the semiconductor package 2003, but a DRAM controller for controlling the DRAM device 2004.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b that are spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, semiconductor chips 2200 disposed on the package substrate 2100, adhesive layers 2300 correspondingly disposed on bottom surfaces of the semiconductor chips 2200, connection structures 2400 that electrically connect the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 on the package substrate 2100 and covering the semiconductor chips 2200 and the connection structures 2400. Although only the first and second semiconductor packages 2003a and 2003b are illustrated, the present inventive concept is not limited thereto. For example, the number of the semiconductor packages is not limited to two, and the electronic system 2000 may include one or more than two semiconductor packages.

The package substrate 2100 may be an integrated circuit board including package upper pads 2130. Each of the semiconductor chips 2200 may include one or more input/output pads 2210. The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 1A. Each of the semiconductor chips 2200 may include stack structures 3210 and vertical structures 3220. Each of the semiconductor chips 2200 may include a semiconductor device according to an embodiment of the present inventive concept which will be discussed below.

In an embodiment of the present inventive concept, the connection structures 2400 may be bonding wires that electrically connect the input/output pads 2210 to the package upper pads 2130. Therefore, on each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other in a wire bonding manner, and may be electrically connected to the package upper pads 2130 of the package substrate 2100. In an embodiment of the present inventive concept, on each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using through silicon via (TSV) instead of the connection structures 2400 or the bonding wires.

In an embodiment of the present inventive concept, the controller 2002 and the semiconductor chips 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chips 2200 may be mounted on an interposer substrate other than the main board 2001, and may be connected to each other through wiring lines formed on the interposer substrate.

FIGS. 1C and 1D illustrate simplified cross-sectional views each showing a semiconductor package according to an embodiment of the present inventive concept. FIGS. 1C and 1D each depicts an exemplary embodiment of the semiconductor package shown in FIG. 1B, conceptually showing a cross-section taken along line I-I′ of the semiconductor package shown in FIG. 1B.

Referring to FIG. 1C, a printed circuit board (PCB) may be used as the package substrate 2100 of the semiconductor package 2003. The package substrate 2100 may include a package substrate body 2120, package upper pads (see 2130 of FIG. 1B) disposed on a top surface of the package substrate body 2120, lower pads 2125 disposed or exposed on a bottom surface of the package substrate body 2120, and internal lines 2135 through which the upper pads 2130 and the lower pads 2125 are electrically connected within the package substrate body 2120. The upper pads 2130 may be electrically connected to the connection structures 2400. The lower pads 2125 may be connected through conductive connection parts 2800 to the wiring patterns 2005 on the main board 2001 of the electronic system 2000, as shown in FIG. 1B.

Each of the semiconductor chips 2200 may include a semiconductor substrate 3010, and may also include a first structure 3100 and a second structure 3200 that are sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including peripheral wiring lines 3110. The second structure 3200 may include a source structure 3205, a stack structure 3210 on the source structure 3205, vertical structures 3220 penetrate the stack structure 3210, bit lines 3240 electrically connected to the vertical structures 3220, and cell contact plugs 3235 electrically connected to the word lines (see WL of FIG. 1A) of the stack structure 3210. Each of the first structure 3100, the second structure 3200, and the semiconductor chips 2200 may further include separation structures which will be discussed below.

Each of the semiconductor chips 2200 may include one or more through lines 3245 that are electrically connected to the peripheral wiring lines 3110 of the first structure 3100 and extend into the second structure 3200. The through line 3245 may be disposed outside the stack structure 3210 and may further be disposed to penetrate the stack structure 3210. Each of the semiconductor chips 2200 may further include input/output pads (see 2210 of FIG. 1B) electrically connected to the peripheral wiring lines 3110 of the first structure 3100.

Referring to FIG. 1D, in a semiconductor package 2003A, each of semiconductor chips 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, a second structure 4200 to which the first structure 4100 is bonded in a wafer bonding manner on the first structure 4100.

The first structure 4100 may include a peripheral circuit region including peripheral wiring lines 4110 and first bonding structures 4150. The second structure 4200 may include a source structure 4205, a stack structure 4210 disposed between the source structure 4205 and the first structure 4100, vertical structures 4220 that penetrate the stack structure 4210, and second bonding structures 4250 that are connected to corresponding vertical structures 4220 and corresponding word lines (see WL of FIG. 1A) of the stack structure 4210. For example, the second bonding structures 4250 may be electrically connected to the vertical structures 4220 and the word lines (see WL of FIG. 1) through bit lines 4240 electrically connected to the vertical structures 4220 and through cell contact plugs 4235 electrically connected to the word lines (see WL of FIG. 1A). The first bonding structures 4150 of the first structure 4100 and the second bonding structures 4250 of the second structure 4200 may be bonded to each other while being in contact with each other. The first and second bonding structures 4150 and 4250 may have their bonding portions formed of, for example, copper (Cu). For example, when the first and second bonding structures 4150 and 4250 are formed of copper (Cu), the first and second bonding structures 4150 and 4250 may be physically and electrically connected to each other by a copper (Cu)-copper (Cu) bonding method.

Each of the first structure 4100, the second structure 4200, and the semiconductor chip 2200a may further include a source structure which will be discussed below. Each of the semiconductor chips 2200a may further include input/output pads (see 2210 of FIG. 1B) electrically connected to the peripheral wiring lines 4110 of the first structure 4100.

The semiconductor chips 2200 of FIG. 1C may be electrically connected to each other through the connection structures (see 2400 of FIG. 1B) shaped like bonding wires, and the same may be true for the semiconductor chips 2200a of FIG. 1D. In an embodiment of the present inventive concept, connection structures such as through silicon vias (TSV) may be used such that semiconductor chips, for example, the semiconductor chips 2200 of FIG. 1C or the semiconductor chips 2200a of FIG. 1D, are electrically connected in a single semiconductor package.

The first structure 3100 of FIG. 1C and the first structure 4100 of FIG. 1D may correspond to a peripheral circuit structure in embodiments which will be discussed below, and the second structure 3200 of FIG. 1C and the second structure 4200 of FIG. 1D may correspond to a cell array structure in embodiments which will be discussed below.

FIG. 2A illustrates a block diagram showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept.

Referring to FIG. 2A, a three-dimensional semiconductor memory device according to an embodiment of present inventive concept may include a peripheral circuit structure PS, a cell array structure CS on the peripheral circuit structure PS, and a wiring structure that connects the cell array structure CS to the peripheral circuit structure PS. The three-dimensional semiconductor memory device of FIG. 2A may correspond to the semiconductor device 1100 of FIG. 1A. The peripheral circuit structure PS may correspond to the first structure 1100F of FIG. 1A, and may include row and column decoder circuits, a page buffer circuit, and control circuits. The cell array structure CS may correspond to the second structure 1100S of FIG. 1A, and may include a plurality of memory blocks BLK0 to BLKn each of which is a data erase unit. Each of the memory blocks BLK0 to BLKn may include a memory cell array having a three-dimensional structure (or vertical structure). For example, the memory blocks BLK0 to BLKn may be connected to a decoder circuit (see 1110 of FIG. 1A) via the word lines (see WL of FIG. 1A), the string selection line (see UL1 of FIG. 1A), the ground selection line (see LL2 of FIG. 1A), and the lower and upper erase control lines (see LL1 and UL2 of FIG. 1A). Further, the memory blocks BLK0 to BLKn may be connected to a page buffer circuit (see 1120 of FIG. 1A) via the bit lines (see BL of FIG. 1A).

FIG. 2B illustrates a circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. The circuit diagram of FIG. 2B depicts a detailed circuit of the configuration shown in the second structure 1100S of FIG. 1A.

Referring to FIG. 2B, in each of the memory blocks BLK0 to BLKn of FIG. 2A, cell strings CSTR may be two-dimensionally arranged along first and second directions D1 and D2 and may extend along a third direction D3. A plurality of cell strings CSTR may be connected in parallel to each of bit lines BL0 to BL2. The plurality of cell strings CSTR may be connected in common to a common source line CSL and provided between the common source line CSL and the bit lines BL0 to BL2. In an embodiment of the present inventive concept, the common source line CSL may be provided in plurality, with the plurality of common source lines CSL supplied with the same voltage, or in some instances independently controlled and supplied with voltages different from each other.

One of the cell strings CSTR may include string selection transistors SST21 and SST11 connected in series, memory cell transistors MCT connected in series, a ground selection transistor GST, and an erase control transistor ECT. The string selection transistors SST21 and SST11 may correspond to the upper transistors UT1 and UT2 of FIG. 1A. The ground selection transistor GST may correspond to the lower transistor LT2 of FIG. 1A. The erase control transistor ECT may correspond to the lower transistor LT1 of FIG. 1A.

Each of the memory cell transistors MCT may include a data storage element. One of the cell strings CSTR may further include dummy cells DMC between the string selection transistor SST11 and the memory cell transistor MCT and between the ground selection transistor GST and the memory cell transistor MCT. Other cell strings CSTR may have an identical or similar structure to that discussed above.

The string selection transistor SST11 may be controlled by a string selection line SSL11, and the string selection transistor SST21 may be controlled by a string selection line SSL21. The memory cell transistors MCT may be controlled by corresponding word lines WL0 to WLn, and the dummy cells DMC may be controlled by corresponding dummy word lines DWL. The ground selection transistor GST may be controlled by a ground selection line GSL0, GSL1, or GSL2, and the erase control transistor ECT may be controlled by an erase control line ECL. For example, the erase control line ECL, the ground selection line GSL0, GSL1, or GSL2, the dummy word lines DWL, the word lines WL0 to WLn, and the string selection lines SSL11, SSL12, or SSL13 and SSL21, SSL22, or SSL23, which are disposed between the common source line CSL and the bit lines BL0 to BL2, may be used as gate electrodes of the erase control transistor ECT, the ground selection transistor GST, the dummy cells DMC, the memory cell transistors MCT, and the string selection transistors SST11 and SST21, respectively.

The memory cell transistors MCT may include gate electrodes at substantially the same distance from the common source line CSL, and the gate electrodes may be connected in common to one of the word lines WL0 to WLn and DWL and thus may have the same potential state. Thus, the word lines WL0 to WLn may act as the gate electrodes of the memory cell transistors MCT. Alternatively, although the gate electrodes of the memory cell transistors MCT are disposed at substantially the same distance from the common source line CSL, the gate electrodes disposed at different rows or columns may be controlled independently of each other. For example, since one cell string CSTR includes the memory cell transistors MCT respectively located at different levels from the common source line CSL, the word lines WL0 to WLn, which may act as gate electrodes for the memory cell transistors MCT, may respectively located at different levels from each other between the common source line CSL and the bit lines BL, and may be provided with potential states the same as or different from each other. In an embodiment of the present inventive concept, the ground and string select transistors GST and SST (SST11 and SST21) and the memory cell transistors MCT may be metal-oxide-semiconductor (MOS) field effect transistors (FETs) using a vertical channel structure as channel regions.

String selection lines SSL11 to SSL13 may be separated from each other. String selection lines SSL21 to SSL23 may be separated from each other. Ground selection lines GSL0 to GSL2 may be separated from each other. The ground selection lines GSL0 to GSL2 may one-to-one correspond to the string selection lines SSL21 to SSL23 (and/or the string selection lines SSL11 to SSL13). Therefore, the ground selection lines GSL0 to GSL2 may be divided corresponding to the string selection lines SSL21 to SSL23, and may correspondingly control the cell strings CSTR. Accordingly, a three-dimensional semiconductor memory device may enhance in program/read/erase operating properties.

FIG. 3 illustrates a plan view showing a three-dimensional semiconductor memory device according to an embodiment of the present inventive concept. FIG. 4A illustrates a plan view showing ground selection gate electrodes according to an embodiment of the present inventive concept. FIG. 4B illustrates a plan view showing string selection gate electrodes according to an embodiment of the present inventive concept. FIG. 4C illustrates a plan view showing a polishing stop pattern according to an embodiment of the present inventive concept. FIG. 4D illustrates a plan view showing cell gate electrodes and an erase control gate electrode according to an embodiment of the present inventive concept. FIG. 5A illustrates a cross-sectional view taken along line A-A′ of FIG. 3. FIG. 5B illustrates a cross-sectional view taken along line B-B′ of FIG. 3. FIG. 5C illustrates a cross-sectional view taken along line C-C′ of FIG. 3. FIG. 6 illustrates an enlarged view showing section P1 of FIG. 5B.

Referring to FIGS. 3 to 6, a cell array structure CS may be disposed on a peripheral circuit structure PS. The cell array structure CS may include blocks BLK that are arranged parallel to a second direction D2. The blocks BLK may correspond to the memory blocks BLK0 to BLKn of FIG. 2A. Most of the blocks BLK may be memory blocks where data program/read/erase operations are performed. Alternatively, a portion of the blocks BLK may be a dummy block where data program/read/erase operations are not performed. The blocks BLK may be correspondingly separated by first separation dielectric lines SL1. FIG. 3 depicts one of the blocks BLK.

The first separation dielectric line SL1 may extend in a first direction D1 that intersects the second direction D2. The first separation dielectric line SL1 may be disposed in a first groove G1. The first separation dielectric line SL1 may have a single-layered or multi-layered structure including at least one selected from, for example, a silicon oxide (SiO₂) layer, a silicon nitride (Si₃N₄) layer, a silicon oxynitride (SiON) layer, and a porous dielectric layer. The blocks BLK may each include a cell array region CAR and a connection region CNR disposed on opposite ends of the cell array region CAR.

A second separation dielectric line SL2 may extend in the first direction D1 while passing through a center of the block BLK, and the second separation dielectric line SL2 may divide the block BLK into two sub-blocks SBLK. The second separation dielectric line SL2 may not be cut on the cell array region CAR and may extend toward the connection region CNR. On the connection region CNR, the second separation dielectric line SL2 may be cut into two pieces. The second separation dielectric line SL2 may be disposed in a second groove G2.

The peripheral circuit structure PS may include a first substrate 103. The first substrate 103 may be a single-crystalline silicon (sc-Si) substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the first substrate 103 may be a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a III-V compound semiconductor substrate, a single-crystalline epitaxial layer grown on a single-crystalline silicon (sc-Si) substrate, a germanium-on-insulator (GOI) substrate, or a combination thereof. The first substrate 103 may have therein a device isolation layer 105 that defines active areas. The active areas may be provided thereon with peripheral transistors PTR. The peripheral transistors PTR may each include a peripheral gate electrode, a peripheral gate dielectric layer, and peripheral source/drain sections disposed in the first substrate 103 adjacent to opposite sides of the peripheral gate dielectric layer. The peripheral circuit structure PS may include various active elements such as transistors, as well as various passive elements such as capacitors, resistors, and inductors. The peripheral transistors PTR may be covered with a peripheral interlayer dielectric layer 107. The peripheral interlayer dielectric layer 107 may have a single-layered or multi-layered structure including at least one selected from, for example, a silicon oxide (SiO₂) layer, a silicon nitride (Si₃N₄) layer, a silicon oxynitride (SiON) layer, and a porous dielectric layer. The peripheral interlayer dielectric layer 107 may be provided therein with peripheral lines 109 and peripheral contacts 33. The peripheral lines 109 and the peripheral contacts 33 may include a conductive layer.

Some of the peripheral lines 109a and the peripheral contacts 33 may be electrically connected to the peripheral transistors PTR. The peripheral lines 109a and the peripheral transistors PTR may constitute the page buffer circuit 1120 and the decoder circuit 1110 of FIG. 1A. The peripheral circuit structure PS may include peripheral conductive pads 30b disposed at top thereof.

An etch stop layer 111 may be disposed on the peripheral circuit structure PS. The etch stop layer 111 may include a material having an etch selectivity with respect to materials of the peripheral interlayer dielectric layer 107 and a second substrate 201 which will be discussed below. For example, the etch stop layer 111 may include silicon nitride (Si₃N₄) or silicon oxide (SiO₂). The etch stop layer 111 may be called an adhesive layer.

Each of the blocks BLK included in the cell array structure CS may include a second substrate 201, a source structure SCL, a first sub-stack structure ST1, a second sub-stack structure ST2, and first, second, and third upper interlayer dielectric layers 205, 208, and 209 that are sequentially stacked. The first sub-stack structure ST1 may include first gate electrodes EGE, GGE, and CGE1, first electrode interlayer dielectric layers 12 that are alternately stacked with the first gate electrodes EGE, GGE, and CGE1, a capping interlayer dielectric layer 15, and a polishing stop pattern TPO. The second sub-stack structure ST2 may include second gate electrodes CGE2 and SGE, second electrode interlayer dielectric layers 22 that are alternately stacked with the second gate electrodes CGE2 and SGE, and an uppermost second electrode interlayer dielectric layer 24 positioned at top of the second sub-stack structure ST2.

The second substrate 201 may be, for example, a single-crystalline silicon (sc-Si) layer, a silicon (Si) epitaxial layer, or a silicon-on-insulator (SOI) substrate. Alternatively, the second substrate 201 may be a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a III-V compound semiconductor substrate, a single-crystalline epitaxial layer grown on a single-crystalline silicon (sc-Si) substrate, a germanium-on-insulator (GOI) substrate, or a combination thereof. The second substrate 201 may be, for example, doped with impurities having a first conductivity type. The first conductivity impurities may be, for example, p-type boron (B). Alternatively, the first conductivity impurities may be n-type arsenic (As) or phosphorus (P). However, the present inventive concept is not limited thereto. In an embodiment of the present inventive concept, the second substrate 201 may include a p-type bulk silicon (Si) substrate and an n-type epitaxial layer grown on the p-type bulk silicon (Si) substrate. In an example embodiment of the present inventive concept, the second substrate 201 may include an n-type bulk silicon (Si) substrate and a p-type or n-type epitaxial layer grown thereon.

Referring to FIGS. 5A to 5C, the first gate electrodes EGE, GGE, and CGE1 may be an erase control gate electrode EGE, a ground selection gate electrode GGE, and first cell gate electrodes CGE1 in a sequence from bottom to top. The second gate electrodes CGE2 and SGE may be second cell gate electrodes CGE2 and a string selection gate electrode SGE in a sequence from bottom to top. The first cell gate electrodes CGE1 and the second cell gate electrodes CGE2 may be referred to as electrode layers.

Referring to FIG. 5A, a middle stack structure MS may collectively indicate layers from the capping interlayer dielectric layer 15 to the second electrode interlayer dielectric layer 22 below the string selection gate electrode SGE. The string selection gate electrode SGE may be positioned on the middle stack structure MS, and the polishing stop pattern TPO, the ground selection gate electrode GGE, and the erase control gate electrode EGE may be disposed below the middle stack structure MS.

The first gate electrodes EGE, GGE, CGE1 and the second gate electrodes CGE2 and SGE may include, for example, at least one selected from, for example, doped semiconductor (e.g., doped silicon (Si)), metal (e.g., tungsten (W), copper (Cu), or aluminum (Al)), conductive metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), and transition metal (e.g., titanium (Ti) or tantalum (Ta)).

The erase control gate electrode EGE may correspond to the erase control line ECL of FIG. 2B. The erase control gate electrode EGE may be divided into two pieces by the second groove G2 that passes between the sub-blocks SBLK as illustrated in FIG. 4D, but the two divided pieces may be connected to each other through a connection part PT1 that is present on the connection region CNR. Therefore, for one block BLK, the erase control gate electrode EGE may have the same potential state.

The first and second cell gate electrodes CGE1 and CGE2 may correspond to the word lines WL0 to WLn and the dummy word line DWL of FIG. 2B. The first and second cell gate electrodes CGE1 and CGE2 may be divided into two pieces by the second groove G2 that passes between the sub-blocks SBLK as illustrated in FIG. 4D, but the two divided pieces may be connected to each other through a connection part PT1 that is present on the connection region CNR. Therefore, for one block BLK, each the first and second cell gate electrodes CGE1 and CGE2 may have the same potential state at a certain height (level).

The ground selection gate electrodes GGE may correspond to the ground selection lines GSL0 to GSL2 of FIG. 2B. The ground selection gate electrodes GGE and the ground selection lines GSL0 to GSL2 of FIG. 2B may be referred to as lower selection lines. The ground selection gate electrodes GGE may have their linear shapes that extend in the first direction D1 and may be spaced apart from each other in the second direction D2. For one sub-block SBLK, the ground selection gate electrodes GGE may include first and second ground selection gate electrodes GGE(1) and GGE(2). For one sub-block SBLK, the first and second ground selection gate electrodes GGE(1) and GGE(2) may be spaced apart at a first interval DS1 from each other across a first lower separation pattern BS1 that is interposed therebetween. The first interval DS1 between the first and second ground selection gate electrodes GGE(1) and GGE(2) may be the same as a first width WT1 of the first lower separation pattern BS1 depicted in FIG. 5A.

In the present embodiment, one first lower separation pattern BS1 may be present in one sub-block SBLK, but two or more first lower separation patterns BS1 may be provided and in this case the number of vertical holes VH and central dummy vertical holes CDVH may be greater than that shown in FIG. 4A. For example, two first lower separation patterns BS1 may be provided in one sub-block SBLK, and in this case three ground selection gate electrodes GGE may be present in one sub-block SBLK. For another example, three first lower separation patterns BS1 may be provided in one sub-block SBLK, and in this case four ground selection gate electrodes GGE may be present in one sub-block SBLK. In some instances, one ground selection line GSL must control two or more string selection lines SSLs may occur. To suppress deterioration of cell operation characteristics and performance, each sub-block SBLK may be divided into as many ground selection gate electrodes GGE as possible.

The string selection gate electrodes SGE may correspond to the string selection lines SSL11 to SSL13 or SSL21 to SSL23 of FIG. 2B. The string selection gate electrodes SGE and the string selection lines SSL11 to SSL13 or SSL21 to SSL23 may be referred to as upper selection lines. The string selection gate electrodes SGE may have their linear shapes that extend in the first direction D1 and may be spaced apart from each other in the second direction D2. For one sub-block SBLK, the string selection gate electrodes SGE may include first and second string selection gate electrodes SGE(1) and SGE(2). For one sub-block SBLK, the first and second string selection gate electrodes SGE(1) and SGE(2) may be spaced apart at a second interval DS2 from each other across an upper separation pattern 9 interposed therebetween. The second interval DS2 between the first and second string selection gate electrodes SGE(1) and SGE(2) may be the same as a second width WT2 of the upper separation pattern 9 depicted in FIG. 5A. The second width WT2 of the upper separation pattern 9 may be smaller than the first width WT1 of the first lower separation pattern BS1. The second interval DS2 between the first and second string selection gate electrodes SGE(1) and SGE(2) may be smaller than the first interval DS1 between the first and second ground selection gate electrodes GGE(1) and GGE(2). In the present embodiment, one upper separation pattern 9 may be present in one sub-block SBLK, but the present inventive concept is not limited thereto. For example, two or more upper separation patterns 9 may be provided and in this case the number of vertical holes VH and central dummy vertical holes CDVH may be greater than that shown in FIG. 4B. For example, three upper separation patterns 9 may be provided in one sub-block SBLK, and in this case four string selection gate electrodes SGE may be present in one sub-block SBLK.

As illustrated in FIG. 4A, the second separation dielectric line SL2 may be interposed between the sub-blocks SBLK. The second separation dielectric line SL2 may be disposed in the second groove G2. For one block BLK, the sub-blocks SBLK may be spaced apart from each other at a third interval DS3. The third interval DS3 may correspond to a width of the second separation dielectric line SL2. The third interval DS3 may be greater than the first interval DS1 and the second interval DS2. For sub-blocks SBLK, the second ground selection gate electrodes GGE(2) may be in contact with the second separation dielectric line SL2. The second ground selection gate electrodes GGE(2) may have their shapes that are mirror-symmetric about the second separation dielectric line SL2.

As illustrated in FIG. 4A, a second separation pattern BS2 may be disposed between neighboring second ground selection gate electrodes GGE(2) on the connection region CNR. The second lower separation pattern BS2 may be disposed in a lower trench BT1. The second lower separation pattern BS2 may not have a linear shape but an island shape when viewed in plan. Between the sub-blocks SBLK, lateral surfaces of the second ground selection gate electrodes GGE(2) may be recessed in the second direction D2 or in a direction opposite to the second direction D2. The recessed lateral surface may correspond to an inner sidewall of the lower trench BT1. A fourth interval DS4 between the inner sidewalls of the lower trench BT1 may correspond to a width in the second direction D2 of the second lower separation pattern BS2. The fourth interval DS4 may be greater than the third interval DS3. The second lower separation pattern BS2 may be interposed between the second separation dielectric lines SL2. The second separation dielectric line SL2 may be in contact with a lateral surface of the second lower separation pattern BS2.

The connection parts PT1 of the erase control gate electrode EGE and the first and second cell gate electrodes CGE(1) and CGE(2) of FIG. 4D may overlap the second lower separation pattern BS2. The first lower separation pattern BS1 and the second lower separation pattern BS2 may include the same dielectric material. For example, the first and second lower separation patterns BS1 and BS2 may include silicon oxide (SiO₂).

The first separation dielectric line SL1 and the second separation dielectric line SL2 may extend in the third direction D3 to penetrate the first gate electrodes EGE, GGE, and CGE1 and the second gate electrodes CGE2 and SGE and to contact sidewalls of the first and second gate electrodes EGE, GGE, CGE1, CGE2, and SGE.

Referring to FIGS. 4C and 5A, the polishing stop pattern TPO may be formed of a material having an etch selectivity with respect to materials of the first electrode interlayer dielectric layers 12, the capping interlayer dielectric layer 15, and the second electrode interlayer dielectric layers 22 and 24. The first electrode interlayer dielectric layers 12, the capping interlayer dielectric layer 15, and the second electrode interlayer dielectric layers 22 and 24 may be formed of, for example, silicon oxide (SiO₂). The polishing stop pattern TPO may be formed of, for example, silicon carbonitride (SiCN). Alternatively, the polishing stop pattern TPO may be formed of silicon oxide (SiO₂). The polishing stop pattern TPO may have a silicon (Si) atomic concentration different from those of the first electrode interlayer dielectric layers 12, the capping interlayer dielectric layer 15, and the second electrode interlayer dielectric layers 22 and 24. For example, a silicon atomic concentration (or density/amount) of the polishing stop pattern TPO may be greater than those of the first electrode interlayer dielectric layers 12, the capping interlayer dielectric layer 15, and the second electrode interlayer dielectric layers 22 and 24. Alternatively, a silicon (Si) atomic concentration (or density/amount) of the polishing stop pattern TPO may increase with decreasing distance from the second substrate 201. For example, the polishing stop pattern TPO may include a material different from those of the first electrode interlayer dielectric layers 12, the capping interlayer dielectric layer 15, and the second electrode interlayer dielectric layers 22 and 24. The polishing stop pattern TPO may be referred to as a first polishing stop layer.

As illustrated in FIGS. 5A to 5C, the polishing stop pattern TPO may have a top surface coplanar with that of the first lower separation pattern BS1 and that of the second lower separation pattern BS2. As illustrated in FIG. 4C, a planar shape of the polishing stop pattern TPO may be coincident with that of each of the ground selection gate electrodes GGE depicted in FIG. 4A. For one sub-block SBLK, the polishing stop pattern TPO may include first and second polishing stop patterns TOP(1) and TPO(2). The first and second polishing stop patterns TPO(1) and TPO(2) may have their linear shapes that extend in the first direction D1 and are spaced apart from each other in the second direction D2.

For one sub-block SBLK, the first lower separation pattern BS1 may be interposed between the first and second polishing stop patterns TPO(1) and TPO(2). The second lower separation pattern BS2 may be disposed between neighboring second polishing stop patterns TPO(2) on the connection region CNR. Between the sub-blocks SBLK, lateral surfaces of the second polishing stop patterns TPO(2) may be recessed in the second direction D2 or in a direction opposite to the second direction D2. The recessed lateral surface may correspond to the inner sidewall of the lower trench BT1.

The source structure SCL may include a first source pattern SC1 interposed between the first electrode interlayer dielectric layer 12 and the second substrate 201, and may also include a second source pattern SC2 interposed between the first source pattern SC1 and the second substrate 201. The first source pattern SC1 may include an impurity-doped semiconductor pattern, for example, polysilicon (p-Si) doped with impurities having a first conductivity type. The second source pattern SC2 may include an impurity-doped semiconductor pattern, for example, impurity-doped polysilicon (p-Si). The second source pattern SC2 may include a semiconductor material different from that of the first source pattern SC1. A conductivity type of impurities doped into the second source pattern SC2 may be the same as that of impurities doped into the first source pattern SC1. A concentration of impurities doped into the second source pattern SC2 may be the same as or different from that of impurities doped into the first source pattern SC1. The source structure SCL may correspond to the common source line CSL of FIG. 1A. In addition, the second substrate 201 may serve as the common source line CSL of FIG. 1A.

On the cell array region CAR of each of the sub-blocks SBLK, cell vertical semiconductor patterns VS may penetrate the electrode interlayer dielectric layers 12, 22, and 24, the capping interlayer dielectric layer 15, the polishing stop pattern TPO, the first gate electrodes EGE, GGE, and CGE1, and the second gate electrodes CGE2 and SGE. For example, the cell vertical semiconductor patterns VS on the cell array region CAR may penetrate the upper selection lines (i.e., the string selection gate electrodes SGE), the middle stack structure MS, the first polishing stop layer (i.e., the polishing stop pattern TPO), the lower selection lines (i.e., the ground selection gate electrodes GGE), and the source structure SCL to be adjacent to the second substrate 201. For example, lower portions of the cell vertical semiconductor patterns VS may be disposed in the second substrate 201. For example, each of the cell vertical semiconductor patterns VS may extend in the third direction D3 and intersect the upper surface of the second substrate 201. Central dummy vertical semiconductor patterns CDVS may penetrate the electrode interlayer dielectric layers 12, 22, and 24, the capping interlayer dielectric layer 15, the polishing stop pattern TPO, the first lower separation pattern BS1, the first cell gate electrodes CGE1, the erase control gate electrode EGE, and the second gate electrodes CGE2 and SGE. For example, the central dummy vertical semiconductor patterns CDVS may penetrate the upper selection lines (i.e., the string selection gate electrodes SGE), the middle stack structure MS, the first polishing stop layer (i.e., the polishing stop pattern TPO), and the first lower separation pattern BS1 to be adjacent to the second substrate 201. For example, lower portions of the central dummy vertical semiconductor patterns CDVS may be disposed in the second substrate 201. For example, each of the central dummy vertical semiconductor patterns CDVS may extend in the third direction D3 and intersect the upper surface of the second substrate 201. The central dummy vertical semiconductor patterns CDVS may be arranged in one row along the first direction D1. The upper separation pattern 9 may be disposed between upper portions of the central dummy vertical semiconductor patterns CDVS. The cell vertical semiconductor patterns VS may be positioned in vertical holes VH. The central dummy vertical semiconductor patterns CDVS may be positioned in central dummy vertical holes CDVH. A gate dielectric layer GO may be interposed between the vertical semiconductor patterns VS and CDVS and the first and second sub-stack structures ST1 and ST2.

The cell vertical semiconductor patterns VS and the central dummy vertical semiconductor patterns CDVS may each have a hollow cup shape. However, the present inventive concept is not limited thereto. In an embodiment of the present inventive concept, the cell vertical semiconductor patterns VS and the central dummy vertical semiconductor patterns CDVS may have various shapes, such as, for example, a cylindrical shape, a rectangular cylindrical shape, and a solid pillar shape. The cell vertical semiconductor patterns VS and the central dummy vertical semiconductor patterns CDVS may each have a sidewall that has an inflection point IFP adjacent to a location between the first sub-stack structure ST1 and the second sub-stack structure ST2.

The cell vertical semiconductor patterns VS and the central dummy vertical semiconductor patterns CDVS may include, for example, a single-crystalline silicon (sc-Si) layer or a polysilicon (p-Si) layer. The cell vertical semiconductor patterns VS and the central dummy vertical semiconductor patterns CDVS may have their insides each of which is filled with a buried dielectric pattern 29. The buried dielectric pattern 29 may have a single-layered or multi-layered structure including, for example, at least one selected from, for example, a silicon oxide (SiO₂) layer, a silicon nitride (Si₃N₄) layer, and a silicon oxynitride (SiON) layer. However, the present inventive concept is not limited thereto. Alternatively, the inner space surrounded by each of the cup-shaped cell vertical semiconductor patterns VS and central dummy vertical semiconductor patterns CDVS may not be filled with the buried dielectric pattern 29, and each of the cup-shaped cell vertical semiconductor patterns VS and central dummy vertical semiconductor patterns CDVS may include a hollow space or an air gap in the inner space defined by each of the cup-shaped cell vertical semiconductor patterns VS and central dummy vertical semiconductor patterns CDVS. A bit-line pad BPD may be disposed on each of the cell vertical semiconductor pattern VS and the central dummy vertical semiconductor pattern CDVS. The bit-line pad BPD may include impurity-doped polysilicon (p-Si) or a metal such as, for example, tungsten (W), aluminum (Al), or copper (Cu).

Referring to FIG. 6, the gate dielectric layer GO may include a tunnel dielectric layer TL, a charge storage layer SN, and a blocking dielectric layer BCL. The charge storage layer SN may be a trap dielectric layer, a floating gate electrode, or a dielectric layer including conductive nano-dots. For example, the charge storage layer SN may include at least one selected from, for example, a silicon nitride (Si₃N₄) layer, a silicon oxynitride (SiON) layer, a silicon-rich nitride (Si_xN_y, x>y) layer, a nano-crystalline silicon (nc-Si) layer, and a laminated trap layer. For example, the tunnel dielectric layer TL may be adjacent to each of the cell vertical semiconductor pattern VS and the central dummy vertical semiconductor pattern CDVS and may surround the outer sidewall of each of the cell vertical semiconductor pattern VS and the central dummy vertical semiconductor pattern CDVS. The tunnel dielectric layer TL may allow charges to tunnel to the charge storage layer SN through the process of Fowler-Nordheim (F-N) tunneling. The tunnel dielectric layer TL may include one of materials each having a bandgap greater than that of the charge storage layer SN, and the blocking dielectric layer BCL may include a high-k dielectric layer such as, for example, an aluminum oxide (Al₂O₃) layer or a hafnium oxide (HfO₂) layer. The gate dielectric layer GO may further include a high-k dielectric layer HL. The high-k dielectric layer HL may be interposed between the blocking dielectric layer BCL and the gate electrodes EGE, GGE, CGE1, CGE2, and SGE. The high-k dielectric layer HL may be interposed between the first and second gate electrodes EGE, GGE, CGE1, CGE2, and SGE and the interlayer dielectric layers 12, 15, 22, and 24. The high-k dielectric layer HL may include a metal oxide layer, such as, for example, a hafnium oxide (HfO₂) layer or an aluminum oxide (Al₂O₃) layer, having a dielectric constant greater than that of a silicon oxide (SiO₂) layer. The second source pattern SC2 may separate a lower portion of the gate dielectric layer GO from an upper portion of the gate dielectric layer GO. For example, the second source pattern SC2 may extend through the gate dielectric layer GO and may contact side surfaces of the cell vertical semiconductor pattern VS and the central dummy vertical semiconductor pattern CDVS. A portion of the first separation dielectric line SL1 may protrude in the second direction D2 toward the first and second gate electrodes EGE, GGE, CGE1, CGE2, and SGE to be interposed between the interlayer dielectric layers 12, 15, 22, and 24. The first separation dielectric lines SL1 may have their uneven structures at sidewalls thereof. Identical or similar to the first separation dielectric lines SL1, the second separation dielectric lines SL2 may have their uneven structures at sidewalls thereof.

The first separation dielectric lines SL1 and the second separation dielectric lines SL2 may be formed of, for example, silicon oxide (SiO₂). In the present embodiment, the first separation dielectric lines SL1 and the second separation dielectric lines SL2 may penetrate the first source pattern SC1 of the source structure SCL, thereby being in contact with the second source pattern SC2 of the source structure SCL. The first separation dielectric lines SL1 and the second separation dielectric lines SL2 may have their bottom surfaces located at the same or different levels. Alternatively, the first separation dielectric lines SL1 and the second separation dielectric lines SL2 may penetrate the source structure SCL to contact the second substrate 201.

A first source connection line CSPLG1 and a second source connection line CSPLG2 may be respectively disposed in the first separation dielectric line SL1 and the second separation dielectric line SL2, thereby being in contact with the second substrate 201 and/or the source structure SCL.

The second upper interlayer dielectric layer 208 may be disposed on the first upper interlayer dielectric layer 205. The second upper interlayer dielectric layer 208 may be provided thereon with first conductive lines BLL that extend in the second direction D2 and are parallel to each other. The first conductive lines BLL may correspond to the bit lines BL of FIG. 1A. On the cell array region CAR, first contacts CT1 may penetrate the first and second upper interlayer dielectric layers 205 and 208 to connect the first conductive lines BLL to the bit-line pads BPD disposed on the cell vertical semiconductor patterns VS.

Referring to FIG. 5C, the first and second sub-stack structures ST1 and ST2 included in each of the blocks BLK may have a stepwise shape on the connection region CNR. For example, the erase control gate electrode EGE and the ground selection gate electrode GGE may have their ends that constitute a stepwise shape. On the connection region CNR, a sidewall of the polishing stop pattern TPO may be aligned with that of the ground selection gate electrode GGE. A residual lower separation pattern BSR may cover the ends of the erase control gate electrode EGE and the ground selection gate electrode GGE. The residual lower separation pattern BSR may be in contact with the sidewall of the polishing stop pattern TPO. The residual lower separation pattern BSR may have a top surface coplanar with that of the polishing stop pattern TPO. The residual lower separation pattern BSR may include a material the same as that of the first and second lower separation patterns BS1 and BS2. As illustrated in FIG. 10, the residual lower separation pattern BSR and an end of the first lower separation pattern BS1 may be connected into a single unitary body.

Referring back to FIG. 5C, the capping interlayer dielectric layer 15 may cover the polishing stop pattern TPO and the residual lower separation pattern BSR. The first cell gate electrodes CGE1 positioned on the capping interlayer dielectric layer 15 may have their ends that constitute a stepwise shape. The ends of the first cell gate electrodes CGE1 may be covered with a first planarized dielectric layer 210.

The second cell gate electrodes CGE2 and the string selection gate electrodes SGE may have their ends that constitute a stepwise shape. For example, first cell gate electrodes CGE1, the second cell gate electrodes CGE2 and the string selection gate electrodes SGE may be staked in a staircase shape in which extension lengths in the first direction D1 may gradually decrease in a stepwise manner from a lowermost level toward an uppermost level. On the connection region CNR, an end of the second sub-stack structure ST2 may be covered with a second planarized dielectric layer 220. The first and second planarized dielectric layers 210 and 220 may include a silicon oxide (SiO₂) layer or a porous dielectric layer. The first, second, and third upper interlayer dielectric layers 205, 208, and 209 may be sequentially stacked on the first and second planarized dielectric layers 210 and 220. In an embodiment of the present inventive concept, the residual lower separation pattern BSR and the first and second planarized dielectric layers 210 and 220 may be formed of the same material such as silicon oxide (SiO₂) and may be connected into a single unitary body as one planarized dielectric layer, and thus, the one planarized dielectric layer may be disposed on the connection region CNR and covering the ends of the lower selection lines (i.e., the ground selection gate electrodes GGE), the end of the first polishing stop layer (i.e., the polishing stop pattern TPO), the end of the middle stack structure MS (which includes electrode layers), and the ends of the upper selection lines (i.e., the string selection gate electrodes SGE). The interlayer dielectric layer 1315 illustrated in FIG. 22 may be similar to the planarized dielectric layer described above.

The first gate electrodes EGE, GGE, and CGE1 and the second gate electrodes CGE2 and SGE may have their ends that are connected to corresponding cell contact plugs CC. The cell contact plugs CC may penetrate the first and second upper interlayer dielectric layers 205 and 208 to correspondingly contact the first gate electrodes EGE, GGE, and CGE1 and the second gate electrodes CGE2 and SGE.

Referring to FIG. 3, edge dummy vertical semiconductor patterns EDVS may penetrate the first and second planarized dielectric layers 210 and 220 and stepwise shaped ends of the first gate electrodes EGE, GGE, and CGE1, the second gate electrodes CGE2 and SGE, and electrode interlayer dielectric layers 12, 22, and 24. The edge dummy vertical semiconductor patterns EDVS may be disposed in corresponding edge dummy vertical holes (see EDVH of FIGS. 4A to 4C).

When viewed in plan, the edge dummy vertical semiconductor patterns EDVS may each have an elliptical shape that is elongated in a certain direction. The edge dummy vertical semiconductor patterns EDVS may each have a cross section identical or similar to that of the cell vertical semiconductor pattern VS depicted in FIG. 6. The edge dummy vertical semiconductor patterns EDVS may have their insides each of which is filled with a buried dielectric pattern 29. A gate dielectric layer GO may be interposed between the edge dummy vertical semiconductor patterns EDVS and the first and second sub-stack structures ST1 and ST2. A bit-line pad BPD may also be disposed on each of the edge dummy vertical semiconductor patterns EDVS. However, the edge dummy vertical semiconductor patterns EDVS may not be connected to the first conductive lines BLL.

Referring still to FIG. 5C, an electrode connection line CL may be disposed on the second upper interlayer dielectric layer 208. On the connection region CNR, edge through vias ETHV may penetrate the first upper interlayer dielectric layer 205, the first and second planarized dielectric layers 210 and 220, the second substrate 201, and the etch stop layer 111, thereby being correspondingly coupled to the peripheral conductive pads 30b. In the present embodiment, the edge through vias ETHV may be spaced apart from the first and second sub-stack structures ST1 and ST2. The edge through vias ETHV may be correspondingly connected to the electrode connection lines CL through third contacts CT3 disposed in the second upper interlayer dielectric layer 208. Therefore, the first gate electrodes EGE, GGE and CGE1 and the second gate electrodes CGE2 and SGE may be connected to, for example, decoder circuit (see 1110 of FIG. 1A) of the peripheral circuit structure PS. A via dielectric pattern SP2 may be interposed between the edge through via ETHV and the first and second planarized dielectric layers 210 and 220 and between the edge through via ETHV and the etch stop layer 111. Also, the via dielectric pattern SP2 may be interposed between the edge through via ETHV and the second substrate 201, and thus, the edge through via ETHV may be electrically insulated from the second substrate 201 by the via dielectric pattern SP2.

The edge through vias ETHV may each include at least one metal selected from, for example, tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), and tantalum (Ta). The via dielectric pattern SP2 may include a dielectric material, such as, for example, silicon oxide (SiO₂), silicon nitride (Si₃N₄), or silicon oxynitride (SiON).

Referring again to FIG. 5C, a substrate ground section WR may be disposed in the second substrate 201 and spaced apart from the edge through vias ETHV. The substrate ground section WR may be doped with first conductivity impurities that are doped into the second substrate 201, and may have an impurity concentration greater than that of the second substrate 201. On the connection region CNR, a substrate contact plug WC may penetrate the first upper interlayer dielectric layer 205, the first and second planarized dielectric layers 210 and 220, the capping interlayer dielectric layer 15, the residual lower separation pattern BSR, and the first electrode interlayer dielectric layer 12, thereby being in contact with the substrate ground section WR.

The electrode connection lines CL may be covered with the third upper interlayer dielectric layer 209. An external terminal CP may be disposed on the third upper interlayer dielectric layer 209. A fourth contact CT4 may penetrate the third and second upper interlayer dielectric layers 209 and 208 to connect the external terminal CP to the substrate contact plug WC. A sidewall of the substrate contact plug WC may be covered with a contact dielectric pattern SP3.

A three-dimensional semiconductor memory device according to the present inventive concept may include the polishing stop pattern TPO to prevent process failure such as dishing issues, and thus the first and second gate electrodes EGE, GGE, CGE1, CGE2, and SGE may be minimized or prevented from breakdown voltage degradation, and the interlayer dielectric layers 12, 15, 22, and 24 may be prevented from variation in thickness. Accordingly, the three-dimensional semiconductor memory device may increase in reliability.

A three-dimensional semiconductor memory device according to the present inventive concept may be configured such that the ground selection gate electrodes GGE may be divided by the first and second lower separation patterns BS1 and BS2 and the second separation dielectric lines SL2, and thus the divided ground selection gate electrodes GGE may one-to-one correspond to the string selection gate electrodes SGE. Therefore, the ground selection lines GSL0 to GSL2 included in the circuit of FIG. 2B may be divided corresponding to the string selection lines SSL21 to SSL23, and may correspondingly control the cell strings CSTR. Thus, deterioration of cell operation characteristics and performance may be suppressed. Accordingly, a three-dimensional semiconductor memory device may enhance in program/read/erase operating properties.

FIGS. 7A to 9A and 11A to 17A illustrate cross-sectional views showing a method of fabricating a three-dimensional semiconductor memory device whose cross-sectional view is shown in FIG. 5A. FIGS. 7B to 9B and 11B to 17B illustrate cross-sectional views showing a method of fabricating a three-dimensional semiconductor memory device whose cross-sectional view is shown in FIG. 5B. FIGS. 7C to 9C and 11C to 17C illustrate cross-sectional views showing a method of fabricating a three-dimensional semiconductor memory device whose cross-sectional view is shown in FIG. 5C. FIG. 10 illustrates a plan view showing a method of fabricating a three-dimensional semiconductor memory device whose plan view is shown in FIG. 3.

Referring to FIGS. 7A to 7C, a peripheral circuit structure PS may be manufactured. A device isolation layer 105 may be formed in a first substrate 103, restricting active areas. Peripheral transistors PTR may be formed on the active areas. A peripheral interlayer dielectric layer 107 may be formed to cover the peripheral transistors PTR, and peripheral contacts 33 and peripheral lines 109 may be formed in the peripheral interlayer dielectric layer 107. The peripheral transistors PTR may each include a peripheral gate electrode, a peripheral gate dielectric layer, and peripheral source/drain sections disposed in the first substrate 103 adjacent to opposite sides of the peripheral gate dielectric layer. The peripheral contacts 33 may be connected to the peripheral source/drain sections. Peripheral conductive pads 30b may be formed at top of the peripheral circuit structure PS. An etch stop layer 111 may be formed on an entire surface of the peripheral circuit structure PS.

A second substrate 201 may be formed on the etch stop layer 111. The second substrate 201 may be formed by forming a semiconductor epitaxial layer or attaching a single-crystalline semiconductor substrate onto the etch stop layer 111. The second substrate 201 may be called a semiconductor layer. The second substrate 201 may be doped with, for example, impurities having a first conductivity type. A substrate ground section WR may be formed in the second substrate 201. The substrate ground section WR may be formed by doping impurities having the first conductivity type, and may have an impurity concentration greater than that of the second substrate 201. The second substrate 201 may include a cell array region CAR and a connection region CNR.

A first buffer layer 16, a first sacrificial layer 17, a second buffer layer 18, and a first source pattern SC1 may be sequentially stacked on the second substrate 201. A first electrode interlayer dielectric layer 12 and another sacrificial layer 14a may be stacked on the first source pattern SC1. On the connection region CNR, the second substrate 201 may be exposed by etching the another sacrificial layer 14a, the first electrode interlayer dielectric layer 12, the first source pattern SC1, the second buffer layer 18, the first sacrificial layer 17, and the first buffer layer 16. In addition, a first electrode interlayer dielectric layer 12, another sacrificial layer 14b, a first electrode interlayer dielectric layer 12, and a polishing stop layer TP may further be formed on the second substrate 201. In the present embodiment, the polishing stop layer TP may be a polysilicon (p-Si) layer. The first and second buffer layers 16 and 18 and the first electrode interlayer dielectric layers 12 may include silicon oxide (SiO₂) that is formed by, for example, atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first sacrificial layer 17 and the another sacrificial layers 14a and 14b may be formed of a silicon nitride (Si₃N₄) layer.

Referring to FIGS. 8A to 8C, a first mask pattern MK1 may be formed on the polishing stop layer TP. The first mask pattern MK1 may be formed of, for example, a photoresist pattern, a spin-on-hardmask (SOH) layer, an amorphous carbon layer (ACL), or a metal layer. The first mask pattern MK1 may be formed by a photolithography process. The first mask pattern MK1 may be used as an etching mask to etch the polishing stop layer TP, the first electrode interlayer dielectric layer 12, and the another sacrificial layer 14b to form lower separation grooves BG1 and a lower trench BT1. Neither the lower separation grooves BG1 nor the lower trench BT1 may expose the another sacrificial layer 14a. For example, bottom surfaces of the lower separation grooves BG1 and the lower trench BT1 may be located within the first electrode interlayer dielectric layer 12 interposed between the another sacrificial layer 14a and the another sacrificial layer 14b. When viewed in plan, the lower separation grooves BG1 and the lower trench BT1 may be formed as shown in FIG. 10. The formation of the lower separation grooves BG1 may divide the another sacrificial layer 14b into a central sacrificial pattern 14b1 and edge sacrificial patterns 14b2 adjacent to an edge of the central sacrificial pattern 14b1. On the connection region CNR, the lower trench BT1 may be positioned on a center of the central sacrificial pattern 14b1.

Referring to FIGS. 9A to 9C, the first mask pattern MK1 may be removed to expose the polishing stop layer TP. A buried dielectric layer may be stacked on the polishing stop layer TP to fill the lower separation grooves BG1 and the lower trench BT1, and the buried dielectric layer may undergo a polishing process such as chemical mechanical polishing (CMP). The buried dielectric layer may be formed of, for example, silicon oxide (SiO₂). The polishing process may simultaneously form a first lower separation pattern BS1 and a second lower separation pattern BS2 in the lower separation groove BG1 and the lower trench BT1, respectively, and top surface of the polishing stop layer TP may be exposed. In addition, on the connection region CNR, a residual lower separation pattern BSR may be formed which is connected to the first lower separation pattern BS1. The residual lower separation pattern BSR may have a top surface coplanar with those of the polishing stop layer TP, the first lower separation pattern BS1 and the second lower separation pattern BS2 after the chemical mechanical polishing (CMP) process. FIGS. 9A, 9B, and 9C may respectively correspond to cross sections taken along lines A-A′, B-B′, and C-C′ of FIG. 10.

A portion of the buried dielectric layer may be formed into the first lower separation pattern BS1, the second lower separation pattern BS2, and the residual lower separation pattern BSR. The polishing stop layer TP may be formed of a polysilicon (p-Si) layer having an excellent etch/polish selectivity with respect to the buried dielectric layer, and thus the first lower separation pattern BS1, the second lower separation pattern BS2, and the residual lower separation pattern BSR may be formed flat without process failure such as dishing issues in which top surfaces thereof are downwardly dented. Therefore, a wavy (or seagull-like) profile may not be formed in subsequent processes, and subsequently-formed electrodes may be minimized or prevented from breakdown voltage degradation, and subsequently-formed interlayer dielectric layers may be prevented from variation in thickness. As such, process defects may be prevented to increase manufacturing yields. Also, after the chemical mechanical polishing (CMP) process, the polishing stop layer TP is left in the assembly structure without being removed, and thus the reverse step risk that may occur while removing the polishing stop layer TP may be eliminated. For example, there may be no step difference when a capping interlayer dielectric layer 15 is subsequently formed. Also, the process steps for manufacturing the three-dimensional semiconductor memory device may be simplified.

Referring to FIGS. 11A to 11C, a thermal oxidation process may be performed to oxidize the polishing stop layer TP formed of a polysilicon (p-Si) layer. Therefore, the polishing stop layer TP may be converted into a polishing stop pattern TPO formed of silicon oxide (SiO₂). In this stage, an oxygen (O) concentration of the polishing stop pattern TPO may be changed based on the degree of oxidation or the penetration depth of oxygen (O). Therefore, a composition of oxygen (O) and silicon (Si) atoms in the polishing stop pattern TPO formed by thermal oxidation may be different from that of oxygen (O) and silicon (Si) atoms in the first electrode interlayer dielectric layers 12 formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). For example, a silicon (Si) atomic concentration (or density/amount) of the polishing stop pattern TPO may be greater than that of the first electrode interlayer dielectric layers 12. Alternatively, a silicon (Si) atomic concentration (or density/amount) of the polishing stop pattern TPO may increase with decreasing distance from the second substrate 201. An oxygen (O) atomic concentration (or density/amount) of the polishing stop pattern TPO may be smaller than that of the first electrode interlayer dielectric layers 12. Alternatively, an oxygen (O) atomic concentration (or density/amount) of the polishing stop pattern TPO may decrease with decreasing distance from the second substrate 201. Accordingly, the polishing stop pattern TPO may include a material different from a material of the first electrode interlayer dielectric layers 12.

Referring to FIGS. 12A to 12C, a capping interlayer dielectric layer 15 may be stacked on the polishing stop pattern TPO, the first lower separation pattern BS1, the second lower separation pattern BS2, and the residual lower separation pattern BSR. As the first lower separation pattern BS1, the second lower separation pattern BS2, and the residual lower separation pattern BSR are formed to have their flat top surface, the capping interlayer dielectric layer 15 may also be formed to have a flat top surface. First electrode interlayer dielectric layers 12 and third sacrificial layers 14e may be alternately stacked on the capping interlayer dielectric layer 15. A first preliminary stack structure PST1 may thus be formed. The first preliminary stack structure PST1 may include various layers 12, 14a, 14b1, 14b2, TPO, 15, and 14e positioned on the second buffer layer 18. The third sacrificial layers 14e may be formed of silicon nitride (Si₃N₄) layer.

Referring to FIG. 12C, a trimming process and an anisotropic etching process may be repeatedly performed such that the first electrode interlayer dielectric layers 12 and the third sacrificial layers 14e on the capping interlayer dielectric layer 15 may be formed to have a stepwise shape at their ends on the connection region CNR. For example, the etching of the first electrode interlayer dielectric layers 12 and the third sacrificial layers 14e and the reducing of the width of a mask pattern that is used as an etch mask may be repeatedly performed during the trimming and anisotropic etching processes. A first planarized dielectric layer 210 may be formed and then a chemical mechanical polishing (CMP) process may be executed to cover the ends of the first electrode interlayer dielectric layers 12 and the third sacrificial layers 14e.

On the cell array region CAR, a plurality of lower holes BH may be formed by etching the first preliminary stack structure PST1, the first source pattern SC1, the second buffer layer 18, the first sacrificial layer 17, the first buffer layer 16, and a portion of the second substrate 201. In this stage, some of the lower holes BH may be formed in the first lower separation patterns BS1. The lower holes BH may be correspondingly filled with lower sacrificial buried patterns BGP. The lower sacrificial buried pattern BGP may be a material having an etch selectivity with respect to the first electrode interlayer dielectric layers 12, the sacrificial layers 14a, 14b1, and 14e, the first source pattern SC1, the second buffer layer 18, the first sacrificial layer 17, the first buffer layer 16, and the second substrate 201. For example, the lower sacrificial buried pattern BGP may have an etch rate significantly higher than etch rates of the other layers, pattern and substrate described above in an etching process, and may be selectively removed in the etching process. For example, the lower sacrificial buried pattern BGP may include, for example, a spin-on-hardmask (SOH) layer, an amorphous carbon layer (ACL), or a silicon germanium (SiGe) layer.

Referring to FIGS. 13A to 13C, a second preliminary stack structure PST2 may be formed by alternately and repeatedly stacking second electrode interlayer dielectric layers 22 and 24 and fourth sacrificial layers 26 on the first preliminary stack structure PST1 and the first planarized dielectric layer 210. The second electrode interlayer dielectric layer 22 and 24 may include a material the same as that of the first electrode interlayer dielectric layers 12. The fourth sacrificial layer 26 may be formed of a material, or silicon nitride (Si₃N₄), the same as that of the third sacrificial layers 14e. A groove may be formed by etching the fourth sacrificial layer 26 and the second electrode interlayer dielectric layers 22 and 24 positioned at top of the second preliminary stack structure PST2, and the groove may be filled with a dielectric layer to form an upper separation pattern 9. The upper separation pattern 9 may be formed to overlap the first lower separation patterns BS1. The upper separation pattern 9 may include a material the same as that of the first lower separation patterns BS1 and that of the electrode interlayer dielectric layers 12, 22, and 24.

A trimming process and an anisotropic etching process may be repeatedly performed such that the second electrode interlayer dielectric layers 22 and 24 and the fourth sacrificial layers 26 may be formed to have a stepwise shape at their ends on the connection region CNR. For example, the etching of the second electrode interlayer dielectric layers 22 and 24 and the fourth sacrificial layers 26 and the reducing of the width of a mask pattern that is used as an etch mask may be repeatedly performed during the trimming and anisotropic etching processes. A second planarized dielectric layer 220 may be formed, and then a chemical mechanical polishing (CMP) process may be executed to cover an end of the second preliminary stack structure PST2. On the cell array region CAR, the second preliminary stack structure PST2 may be etched to form upper holes UH that correspondingly expose the lower sacrificial buried patterns BGP. One or more of the upper holes UH may be formed in the upper separation pattern 9. The upper holes UH may be filled with upper sacrificial buried patterns UGP. The upper sacrificial buried patterns UGP may include, for example, a spin-on-hardmask (SOH) layer, an amorphous carbon layer (ACL), or a silicon germanium (SiGe) layer.

On the cell array region CAR, the upper holes UH and the lower holes BH that overlap each other may constitute vertical holes VH and central dummy vertical holes CDVH. The central dummy vertical holes CDVH may be disposed between the vertical holes VH and may be arranged along the first direction D1. The central dummy vertical holes CDVH may be formed in the first lower separation patterns BS1. On the connection region CNR, edge dummy vertical holes EDVH may be formed simultaneously with the vertical holes VH and the central dummy vertical holes CDVH. In an embodiment of the present inventive concept, instead of forming the lower holes BH first then forming the upper holes UH, the first preliminary stack structure PST1 and the second preliminary stack structure PST2 may be formed first, then the vertical holes VH may be formed by sequentially etching the second preliminary stack structure PST2 and the first preliminary stack structure PST1 to expose the second substrate 201.

Referring to FIGS. 14A to 14C, the upper sacrificial buried pattern UGP and the lower sacrificial buried pattern BGP may be removed from the vertical holes VH and the central dummy vertical holes CDVH to expose inner surfaces of the vertical holes VH, the central dummy vertical holes CDVH, and the edge dummy vertical holes EDVH. A gate dielectric layer GO may be formed in the vertical holes VH, the central dummy vertical holes CDVH, and the edge dummy vertical holes EDVH. As shown in FIG. 6, a blocking dielectric layer BCL, a charge storage layer SN, and a tunnel dielectric layer TL may be sequentially conformally stacked on the first preliminary stack structure PST1 and the second preliminary stack structure PST2 in which the vertical holes VH and the central dummy vertical holes CDVH are formed. A silicon (Si) layer may be conformally deposited on the gate dielectric layer GO. A dielectric layer may be formed on the silicon (Si) layer to thereby fill the vertical holes VH, the central dummy vertical holes CDVH, and the edge dummy vertical holes EDVH. An etch-back or CMP process may be performed to form cell vertical semiconductor patterns VS, central dummy vertical semiconductor patterns CDVS, and edge dummy vertical semiconductor patterns EDVS in the vertical holes VH, the central dummy vertical holes CDVH, and the edge dummy vertical holes EDVH, respectively. Upper portions of the cell vertical semiconductor patterns VS, the central dummy vertical semiconductor patterns CDVS, and the edge dummy vertical semiconductor patterns EDVS may be partially removed, and then removed portions may be filled with an impurity-doped silicon (Si) layer to form bit-line pads BPD. Accordingly, a preliminary cell array structure PCS may be formed.

Referring to FIGS. 15A to 15C, a first upper interlayer dielectric layer 205 may be stacked on the second preliminary stack structure PST2. The first upper interlayer dielectric layer 205, the second preliminary stack structure PST2, the first preliminary stack structure PST1, the first source pattern SC1, and the second buffer layer 18 may be sequentially etched to form first and second grooves G1 and G2 that expose the first sacrificial layer 17. A mask pattern may be formed on the first upper interlayer dielectric layer 205, and may be used as an etch mask for etching the first upper interlayer dielectric layer 205, the second preliminary stack structure PST2, the first preliminary stack structure PST1, the first source pattern SC1, and the second buffer layer 18. After the first and second grooves G1 and G2 are formed, the mask pattern may be removed. As illustrated in FIG. 4A or 4C, the second grooves G2 may be formed to expose a sidewall of the second lower separation pattern BS2. The formation of the second grooves G2 may divide the central sacrificial pattern 14b1 of FIG. 10 into two pieces. A first empty space ER1 may be formed by removing the second buffer layer 18, the first sacrificial layer 17, and the first buffer layer 16 through the first and second grooves G1 and G2.

When the first empty space ER1 is formed, a portion of the gate dielectric layer GO may be removed to expose lower sidewalls of the cell vertical semiconductor pattern VS, the central dummy vertical semiconductor pattern CDVS, and the edge dummy vertical semiconductor pattern EDVS. When the first empty space ER1 is formed, the cell vertical semiconductor pattern VS, the central dummy vertical semiconductor pattern CDVS, and the edge dummy vertical semiconductor pattern EDVS may support and prevent collapse of the preliminary cell array structure PCS.

Referring to FIGS. 16A to 16C, a second source layer may be provided through the first and second grooves G1 and G2 to conformally stacked so as to fill the first empty space ER1, and then an anisotropic etching process may be performed to remove the second source layer from the first and second grooves G1 and G2 and to leave the second source layer in the first empty space ER1, thereby forming a second source pattern SC2. Accordingly, the first source pattern SC1 and the second source pattern SC2 may constitute a source structure SCL. The portion of the second source pattern SC2 adjacent to each of the cell vertical semiconductor pattern VS, the central dummy vertical semiconductor pattern CDVS, and the edge dummy vertical semiconductor pattern EDVS may protrude upward to replace a portion of the gate dielectric layer GO interposed between the first source pattern SC1 and each of the cell vertical semiconductor pattern VS, the central dummy vertical semiconductor pattern CDVS, and the edge dummy vertical semiconductor pattern EDVS, and may protrude downward to replace a portion of the gate dielectric layer GO interposed between the second substrate 201 and each of the cell vertical semiconductor pattern VS, the central dummy vertical semiconductor pattern CDVS.

Referring to FIGS. 17A to 17C, the another sacrificial layer 14a, the central sacrificial pattern 14b1, the edge sacrificial patterns 14b2, the third sacrificial layers 14e, and the fourth sacrificial layer 26 may be removed through the first and second grooves G1 and G2, such that second empty spaces may be formed between the electrode interlayer dielectric layers 12, 22, and 24. A conductive layer may be conformally stacked to fill the second empty spaces through the first and second grooves G1 and G2. An anisotropic etching process may be performed to remove the conductive layer from the first and second grooves G1 and G2, such that first and second gate electrodes EGE, GGE, CGE1, CGE2, and SGE may be formed in the second empty spaces. Therefore, a first sub-stack structure ST1 and a second sub-stack structure ST2 may be formed. Before the conductive layer is stacked to form the first and second gate electrodes EGE, GGE, CGE1, CGE2, and SGE, a high-k dielectric layer HL of FIG. 6 may be formed. A dielectric layer may be conformally stacked and then anisotropically etched to form first and second separation dielectric lines SL1 and SL2 to cover sidewalls of the first and second grooves G1 and G2. A conductive layer may be stacked to form a first source connection line CSPLG1 and a second source connection line CSPLG2 that fill the first and second grooves G1 and G2. Subsequently, typical processes may be executed to fabricate a three-dimensional semiconductor memory device discussed with reference to FIGS. 3 to 6.

As the polishing stop pattern TPO is converted into silicon oxide (SiO₂) in the thermal oxidation process, the polishing stop pattern TPO may not be removed when removing the another sacrificial layer 14a, the central sacrificial pattern 14b1, the edge sacrificial patterns 14b2, the third sacrificial layers 14e, and the fourth sacrificial layer 26.

When the polishing stop pattern TPO remains as a polysilicon (p-Si) layer without being oxidized, the polishing stop pattern TPO may become a dummy electrode to adversely affect an operation of a three-dimensional semiconductor memory device that is eventually fabricated. In the present embodiment, the polishing stop pattern TPO may be oxidized into a dielectric layer to solve the problems mentioned above. Since only oxidized polysilicon (p-Si) remains, there is no concern of unwanted electrical connection of the polishing stop pattern TPO with any adjacent conductive components.

FIGS. 18A and 19A illustrate cross-sectional views showing a method of fabricating a three-dimensional semiconductor memory device whose plan view is shown in FIG. 5A. FIGS. 18B and 19B illustrate cross-sectional views showing a method of fabricating a three-dimensional semiconductor memory device whose cross-sectional view is shown in FIG. 5B. FIGS. 18C and 19C illustrate cross-sectional views showing a method of fabricating a three-dimensional semiconductor memory device whose cross-sectional view is shown in FIG. 5C.

Referring to FIGS. 18A to 18C, in the step of FIGS. 7A to 7C, a polishing stop pattern TPO instead of the polishing stop layer TP may be conformally formed on the first electrode interlayer dielectric layer 12. In this stage, the polishing stop pattern TPO may be formed of a dielectric material having an etch/polish selectivity with respect to the first electrode interlayer dielectric layer 12 and a buried dielectric layer which will be formed subsequently. In the present embodiment, the polishing stop pattern TPO may be formed of, for example, silicon carbonitride (SiCN).

Referring to FIGS. 19A to 19C, a first mask pattern MK1 may be formed on the polishing stop pattern TPO, and identically or similarly to that discussed with reference to FIGS. 8A to 8C, a lower separation groove BG1 and a lower trench BT1 may be formed. Subsequently, as discussed with reference to FIGS. 9A to 9C and 10, a buried dielectric may be stacked and then a chemical mechanical polishing (CMP) process may be performed to form first and second lower separation patterns BS1 and BS2 and a residual lower separation pattern BSR that respectively fill the lower separation groove BG1 and the lower trench BT1.

In the present embodiment, as the polishing stop pattern TPO is formed of silicon carbonitride (SiCN) or a dielectric layer, subsequent processes discussed with reference to FIGS. 12A to 17C may be immediately performed without executing an oxidation process discussed with reference to FIGS. 11A to 11C, with the result that a three-dimensional semiconductor memory device may be fabricated as discussed with reference to FIGS. 3 to 6.

In a fabrication method according to the present embodiment, because the polishing stop pattern TPO is formed of silicon carbonitride (SiCN) or a dielectric layer, it may not be required to remove the polishing stop pattern TPO. Therefore, process steps may become simplified, and a lower structure may have no step difference when the capping interlayer dielectric layer 15 is formed. Accordingly, the capping interlayer dielectric layer 15 may be formed to have a flat top surface, and thus process failure may be prevented. For example, subsequently-formed interlayer dielectric layers may be prevented from variation in thickness.

In a fabrication method according to the present embodiment, as the polishing stop pattern TPO is formed of silicon carbonitride (SiCN), the polishing stop pattern TPO may have an excellent etch selectivity with respect to silicon nitride (Si₃N₄). The polishing stop pattern TPO may not be removed when removing the another sacrificial layer 14a, the central sacrificial pattern 14b1, the edge sacrificial patterns 14b2, the third sacrificial layers 14e, and the fourth sacrificial layer 26.

FIG. 20 illustrates a cross-sectional view taken along line C-C′ of FIG. 3.

Referring to FIG. 20, a second polishing stop layer 27 may be positioned on the first sub-stack structure ST1 in the structure of FIG. 5C. Referring to FIGS. 5A and 20, the middle stack structure MS may include a first middle stack structure, which includes a lower portion of the middle stack structure MS within the first sub-stack structure ST1, and a second middle stack structure, which includes an upper portion of the middle stack structure MS within the second sub-stack structure ST2, positioned on the first middle stack structure. The second polishing stop layer 27 may be disposed between the first middle stack structure and the second middle stack structure. The second polishing stop layer 27 may be formed of silicon carbonitride (SiCN). Alternatively, the second polishing stop layer 27 may be formed of silicon oxide (SiO₂). For example, a silicon (Si) atomic concentration (or density/amount) of the second polishing stop layer 27 may be greater than those of the first electrode interlayer dielectric layers 12. Alternatively, a silicon (Si) atomic concentration (or density/amount) of the second polishing stop layer 27 may increase with decreasing distance from the second substrate 201. For example, the second polishing stop layer 27 may include a material the same as a material of the first polishing stop layer (i.e., the polishing stop pattern TPO). The second polishing stop layer 27 may have a top surface coplanar with that of the first planarized dielectric layer 210. The second polishing stop layer 27 may prevent dishing issues when a chemical mechanical polishing (CMP) process is performed on the first planarized dielectric layer 210 in the step of FIGS. 12A to 12C.

FIG. 21 illustrates a cross-sectional view taken along line C-C′ of FIG. 3.

Referring to FIG. 21, a third polishing stop layer 19 may be positioned on the second sub-stack structure ST2 in the structure of FIG. 20. The third polishing stop layer 19 may be formed of silicon carbonitride (SiCN). Alternatively, the third polishing stop layer 19 may be formed of silicon oxide (SiO₂). For example, a silicon (Si) atomic concentration (or density/amount) of the third polishing stop layer 19 may be greater than those of the second electrode interlayer dielectric layers 22 and 24. Alternatively, a silicon (Si) atomic concentration (or density/amount) of the third polishing stop layer 19 may increase with decreasing distance from the second substrate 201. The third polishing stop layer 19 may have a top surface coplanar with that of the second planarized dielectric layer 220. For example, the third polishing stop layer 19 may cover the upper selection lines (i.e., the string selection gate electrodes SGE), and may include a material the same as a material of the first polishing stop layer (i.e., the polishing stop pattern TPO). The third polishing stop layer 19 may prevent dishing issues when a chemical mechanical polishing (CMP) process is performed on the second planarized dielectric layer 220 in the step of FIGS. 13A to 13C.

FIG. 22 illustrates a cross-sectional view showing a semiconductor device according to an embodiment of the present inventive concept.

Referring to FIG. 22, a semiconductor device 1400 may have a chip-to-chip (C2C) structure. The C2C structure may be fabricated by forming on a first wafer an upper chip including a cell array structure CELL; forming, on a second wafer different from the first wafer, a lower chip including a peripheral circuit structure PERI; and then using a bonding method to connect the upper and lower chips to each other. For example, the bonding method may indicate a way that electrically connects a bonding metal formed an uppermost metal layer of the upper chip to a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of, for example, aluminum (Al) or tungsten (W). In an embodiment of the present inventive concept, the upper chip and the lower chip may be connected directly to each other by a hybrid bonding method. For example, when the bonding metals of the upper and lower chips are formed of copper (Cu), the bonding metals of the upper and lower chips may be physically and electrically connected to each other by a copper (Cu)-copper (Cu) bonding method. In addition, a surface of an interlayer dielectric layer of the upper chip and a surface of an interlayer dielectric layer of the lower chip may be bonded to each other by a dielectric material-dielectric material bonding method.

Each of the peripheral circuit structure PERI and the cell array structure CELL of the semiconductor device 1400 may include an outer pad bonding area PA, a word-line bonding area WLBA, and a bit-line bonding area BLBA.

The peripheral circuit structure PERI may include a first substrate 1210, an interlayer dielectric layer 1215, a plurality of circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c correspondingly connected to the plurality of circuit elements 1220a, 1220b, and 1220c, and second metal layers 1240a, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230c. In an embodiment of the present inventive concept, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten (W) whose electrical resistivity is relatively higher, and the second metal layers 1240a, 1240b, and 1240c may be formed of copper (Cu) whose electrical resistivity is relatively lower.

The first metal layers 1230a, 1230b, and 1230c and the second metal layers 1240a, 1240b, and 1240c are shown and discussed in this description, but the present inventive concept is not limited thereto, and one or more metal layers may further be formed on the second metal layers 1240a, 1240b, and 1240c. At least one of the metal layers formed on the second metal layers 1240a, 1240b, and 1240c may be formed of aluminum (Al) whose electrical resistivity is greater than that of copper (Cu) used for forming the second metal layers 1240a, 1240b, and 1240c.

The interlayer dielectric layer 1215 may be disposed on the first substrate 1210 so as to cover the plurality of circuit elements 1220a, 1220b, and 1220c, the first metal layers 1230a, 1230b, and 1230c, and the second metal layers 1240a, 1240b, and 1240c, and may include a dielectric material, such as, for example, silicon oxide (SiO₂) or silicon nitride (Si₃N₄).

A lower bonding metal 1271b and 1272b may be formed on the second metal layer 1240b of the word-line bonding area WLBA. On the word-line bonding area WLBA, the lower bonding metal 1271b and 1272b of the peripheral circuit structure PERI may be electrically bonded and connected to an upper bonding metal 1371b and 1372b of the cell array structure CELL, and the lower bonding metal 1271b and 1272b and the upper bonding metal 1371b and 1372b may be formed of, for example, aluminum (Al), copper (Cu), or tungsten (W).

The cell array structure CELL may correspond to the cell array structure CS discussed with reference to FIGS. 3 to 21. The cell array structure CELL may provide at least one memory block. The cell array structure CELL may include a second substrate 1310 and a common source line 1320. The second substrate 1310 may be provided thereon with a plurality of word lines 1330 (or 1331 to 1338) arranged along a direction (third direction D