FIG. 12, final target curves for {circle around (1)} through {circle around (4)} of FIG. 12 may all have the same shape.

However, when implemented as actual patterns on a substrate, peripheral target patterns that are not above or below, or on either side of, the interest target pattern may affect the interest target pattern. That is, defects may occur in the actual patterns on the substrate.

On the contrary, the shapes of the final target curves for {circle around (1)} through {circle around (4)} of FIG. 13 may be made to differ from one another in consideration that the layout of the peripheral target patterns around the interest target pattern differs from {circle around (1)} to {circle around (2)} to {circle around (3)} to {circle around (4)} of FIG. 13.

Specifically, the size to which an initial target curve is biased in directions (as indicated by solid line arrows) where the peripheral target patterns are arranged with respect to the interest target pattern may differ from the size to which the initial target curve is biased in directions where the peripheral target patterns are not arranged with respect to the interest target pattern, as indicated by dotted line arrows. Accordingly, the shapes of the final target curves for {circle around (1)} through {circle around (4)} of FIG. 13 may all differ from one another.

As the shape of a final target curve varies depending on the layout of peripheral target patterns around an interest target pattern, the occurrence of defects in actual patterns on a substrate can be prevented.

FIG. 14 is a flowchart illustrating a method of fabricating a mask according to some example embodiments of the present disclosure. FIGS. 15 through 18 illustrate the method of fabricating a mask according to some example embodiments of the present disclosure.

Referring to FIG. 14, a target curve is generated (S100).

The target curve may correspond to the final target curve described above with reference to FIGS. 1 through 11 (e.g., the final target curve F_TC of FIG. 8). That is, the target curve may be generated based on the bias control points BCP1, BCP2 of FIG. 6.

Referring to FIGS. 14 and 15, OPC is performed on an initial design mask IN_DM (S200).

The initial design mask IN_DM may be associated with the initial target pattern IN_TP of FIG. 3.

Specifically, the initial design mask IN_DM is generated. A contour C1_DM of the initial design mask IN_DM is extracted by performing OPC. The contour C1_DM of the initial design mask IN_DM may be extracted through simulation by inputting mask data regarding the initial design mask IN_DM to an OPC model.

Various basic data may be input for OPC. Here, the basic data may include mask data regarding fragments. Also, the basic data may include data such as the thickness, the refractive index, and the dielectric constant of photoresist (PR) and source map data regarding the type of an illumination system. However, the basic data is not particularly limited. The mask data may include not only data regarding fragments, but also the shapes, locations, and types of measurements (e.g., space or line measurements) of patterns.

The contour C1_DM of the initial design mask IN_DM is the result of OPC. The contour C1_DM of the initial design mask IN_DM may correspond to the shape of a pattern formed on a water through exposure using a photomask. That is, the shape of the contour C1_DM of the initial design mask IN_DM may be transferred onto a wafer.

Before an OPC process for extracting the contour C1_DM of the initial design mask IN_DM, a final target curve F_TC is generated.

Referring to FIGS. 14 through 16, the initial design mask IN DM is updated using the final target curve F_TC (S300).

A first updated design mask UP1_DM, which is obtained by updating the initial design mask IN_DM, is generated using the final target curve F_TC and the contour C1_DM of the initial design mask IN_DM.

A first difference between the final target curve F_TC and the contour C1_DM of the initial design mask IN_DM is calculated. The mask data of the initial design mask IN_DM may be updated with the use of the first difference. As a result, the first updated design mask UP1_DM may be generated.

Referring to FIG. 16, a contour C2_DM of the first updated design mask UP1_DM is extracted by performing OPC on the first updated design mask UP1_DM.

A second updated design mask UP2_DM is generated by updating the first updated design mask UP1_DM with the use of the final target curve F_TC and the contour C2_DM of the first updated design mask UP1_DM.

OPC for extracting the contour of a design mask may be repeatedly performed. Then, the design mask may be repeatedly updated by calculating the contour obtained by OPC and the final target curve F_TC.

For convenience, it is assumed that the second updated design mask UP2_DM is a final design mask F_DM, however, in some example embodiments, additional updated design masks may be generated

Referring to FIGS. 14, 17, and 18, the final design mask F_DM is generated (S400).

The final design mask F_DM may be generated by repeatedly performing OPC.

For example, a contour C3_DM of the second updated design mask UP2_DM is extracted by performing OPC. The second updated design mask UP2_DM may be the final design mask DM if the difference between the final target curve F_TC and the contour C3_DM of the second updated design mask UP2_DM is less than a reference value.

In another example, the user may determine the number of OPC processes to be performed during the fabrication of a mask in advance. If the number of OPC processes that have been performed is the reference value, a mask obtained by the last OPC process may be the final design mask F_DM. If the reference value is 3, the second updated design mask UP2_DM may be the final design mask F_DM.

Referring to FIGS. 14 and 18 photomask is fabricated based on the final design mask F_DM (S500).

The photomask may be as illustrated in FIG. 22.

FIG. 19 is a block diagram of an apparatus for fabricating a mask according to some example embodiments of the present disclosure.

Referring to FIG. 19, the apparatus may include a processor 10, a working memory 30, an input/output (I/O) device 50, an auxiliary storage device 70, and a system interconnector 90.

For example, the apparatus may be an apparatus dedicated for the method of fabricating a mask according to some example embodiments of the present disclosure or may be an apparatus dedicated for conducting semiconductor design, including an apparatus dedicated for the method of fabricating a mask according to some example embodiments of the present disclosure. For example, the apparatus may include various design and design simulation programs.

The processor 10 may execute software (e.g., application programs, an operating system (OS), and device drivers) to be run in the apparatus. Although not specifically illustrated, the processor 10 may execute an OS loaded in the working memory 30. The processor 10 may execute various application programs to be run on the OS. For example, the processor 10 may be a central processing unit (CPU), a microprocessor, an application processor (AP), or an arbitrary processing device similar to an AP.

The OS and the application programs may be loaded in the working memory 30. Although not specifically illustrated, an OS image may be loaded into the working memory 30 in accordance with a booting sequence during the booting of the apparatus. I/O operations for the apparatus may be supported by the OS. Similarly, the application programs may be loaded into the working memory 30 to provide basic services or services selected by the user. A design tool 32 for semiconductor design and/or an OPC tool 34 for generating a target curve and fabricating a mask may be loaded from the auxiliary storage device 70 into the working memory 30.

The design tool 32 may be equipped with a bias function for changing the shapes and locations of particular layout patterns differently from a design rule. Also, the design tool 32 may perform design rule check (DRC) under changed bias data conditions. For example, the working memory 30 may be a volatile memory such as a dynamic random-access memory (DRAM) or a static random-access memory (SRAM) or may be a nonvolatile memory (non-transitory memory) such as a flash memory, a phase-change random-access memory (PRAM), a resistive random-access memory (RRAM), a nano-floating gate memory (NFGM), a polymer random-access memory (PoRAM), a magnetic random-access memory (MRAM), or a ferroelectric random-access memory (FRAM).

The I/O device 50 may control user input and output from user interface devices. For example. the 1/0 device 50 may be equipped with input means such as a keyboard, a keypad, a mouse, or a touchscreen and may thus be able to receive information from the user. The user may receive information regarding semiconductor areas or data paths that require the calibration of operating characteristics, via the I/O device 50. Also, the I/O device 50 may be equipped with output means such as a printer or a display and may thus be able to display how the design tool 32 and/or the OPC tool 34 are being processed and the results thereof.

The auxiliary storage device 70 may be provided as a storage medium for the apparatus. The auxiliary storage device 70 may store the application programs, the OS image, and various data. The auxiliary storage device 70 may be provided as a mass storage device such as a memory card (e.g., an MMC, an eMMC, an SD, or a MicroSD), a hard disk drive (HDD), a solid-state drive (SSD), or a universal flash storage (UFS).

The system interconnector 90 may be a system bus for providing a network inside the apparatus. The processor 10, the working memory 30, the I/O device 50, and the auxiliary storage device 70 may be electrically connected via the system interconnector 90 and may thus be able to exchange data with one another. However, the present disclosure is not limited to this, and various other mediation means than the system interconnector 90 may be further provided for efficiency.

FIG. 20 is a flowchart illustrating a method of fabricating a semiconductor device according to some example embodiments of the present disclosure.

Referring to FIG. 20, a high-level design process for a semiconductor device is performed (S1000).

The high-level design process may refer to describing a target integrated circuit (IC) in a high-level computer language such as, for example, C programming language. Circuits designed by the high-level design process may be expressed in further detail by register transfer level (RTL) coding or simulation. Code generated by RTL coding may be converted into a netlist to be synthesized into an entire semiconductor device. Synthesized schematic circuits are verified by a simulation tool and ay be calibrated depending on the result of the verification.

The design layout of layers included in the semiconductor device is obtained (S1100),

In other words, a layout design process may be performed to implement a logically completed semiconductor device on a silicon substrate. For example, the layout design process may be performed based on a schematic circuit prepared by the high-level design process or a netlist corresponding to the schematic circuit, The layout design process may include a routing operation of placing and connecting various standard cells provided by a cell library, in accordance with a predetermined (or, alternatively, desired) design rule,

The cell library for the layout design process may include information on operations, speeds and power consumption of the standard cells. A cell library for representing the layout of a circuit having a specific gate level may be defined in most layout design tools.

Here, the term “layout” may refer to a procedure for defining the shapes or sizes of patterns for configuring transistors and metal wiring, which are to be actually formed on a silicon substrate. For example, layout patterns, such as P-type metal-oxide semiconductor (PMOS) transistors, N-type metal-oxide semiconductor (NMOS) transistors, N-well region, gate electrodes, and metal wiring to be arranged thereon, may be placed to form an inverter circuit on a silicon substrate. To this end, an appropriate inverter may be searched for and selected from inverters defined in advance in the cell library.

A routing operation may be performed on selected and placed standard cells. Specifically, upper wiring may be routed on the selected and placed standard cells. As a result of the routing operation, standard cells may be connected to one another to fit the design. S1000 and S1100 may be performed automatically or manually by the design tool 32 of FIG. 19. The placement and routing of standard cells may be performed automatically via a separate placement and routing tool.

After the routing operation, a verification operation may be performed on the layout to verify whether the layout violates the design rule. The verification operation may include DRC for verifying whether the layout conforms to the design rule, electrical rule check (ERC) for verifying whether there are any electrical disconnections in the layout, and Layout Vs Schematic (LVS) check for verifying whether the layout coincides with a gate-level netlist.

Thereafter, a photomask is fabricated (S1200). S1200 may be performed by the method of fabricating a mask according to some example embodiments of the present disclosure, described above with reference to