100 may further include a third insulating layer and a third wiring layer. The third insulating layer covers second insulating layer 7 and second wiring layer 8. The third wiring layer is electrically connected to second wiring layer 8. The third wiring layer includes a third layer section. The third layer section covers second wiring layer 8. The third layer section has a portion overlying second layer section 81 of second wiring layer 8 with the third insulating layer interposed. Organic layer OL may cover the third wiring layer.

Referring now to FIG. 3 to FIG. 5, semiconductor package 100 according to the first embodiment will be described in detail.

As shown in FIG. 3, semiconductor element 1 includes a plurality of first semiconductor sections 1a and a plurality of second semiconductor sections 1b. In FIG. 3, sealing section 9 is not shown for convenience of explanation.

Conductive plate 2 includes a plurality of first conductive sections 2a, a second conductive section 2b, and a plurality of third conductive sections 2c. Second conductive section 2b is arranged between first semiconductor sections 1a and second semiconductor sections 1b. A plurality of third conductive sections 2c are arranged on a side opposite to first semiconductor sections 1a with respect to second conductive section 2b.

Heat spreader 4 includes a first heat spreader section 4a and a second heat spreader section 4b. First heat spreader section 4a is arranged at a distance from first heat spreader section 4a. A plurality of first semiconductor sections 1a, a plurality of first conductive sections 2a, and second conductive section 2b are bonded to first heat spreader section 4a. A plurality of second semiconductor sections 1b and a plurality of third conductive sections 2c are bonded to second heat spreader section 4b.

As shown in FIG. 4, first wiring layer 6 includes a plurality of first wiring portions 6a, second wiring portion 6b, a plurality of third wiring portions 6c, a plurality of fourth wiring portion 6d, and a plurality of fifth wiring portions 6e. In FIG. 4, the outer shapes of the portions of semiconductor element 1, conductive plate 2, and heat spreader 4 on which other members are overlaid are shown by broken lines. Each of a plurality of first wiring portions 6a is connected to the corresponding one of a plurality of first semiconductor sections 1a. Second wiring portion 6b is bonded to second conductive section 2b and each of a plurality of second semiconductor sections 1b. Each of a plurality of third wiring portions 6c is connected to the corresponding one of a plurality of first conductive sections 2a. Each of a plurality of fourth wiring portions 6d is connected to the corresponding one of a plurality of second semiconductor sections 1b. Each of a plurality of fifth wiring portions 6e is connected to the corresponding one of a plurality of third conductive sections 2c.

First wiring layer 6 has an area equal to or larger than semiconductor element 1. Specifically, second wiring portion 6b has an area equal to or larger than that of semiconductor element 1. First layer section 61 has an area equal to or larger than that of semiconductor element 1.

As shown in FIG. 5, each of a plurality of first wiring portions 6a, a plurality of third wiring portions 6c, a plurality of fourth wiring portions 6d, and a plurality of fifth wiring portions 6e is partially exposed from second insulating layer 7. In FIG. 5, the outer shapes of the portions of first insulating layer 5 and first wiring layer 6 on which other members are overlaid are shown by dashed-dotted lines. Each of a plurality of first wiring portions 6a, a plurality of second wiring portions 6b, a plurality of fourth wiring portions 6d, and a plurality of fifth wiring portions 6e is connectable to an external terminal. Each of a plurality of first wiring portions 6a, a plurality of third wiring portions 6c, a plurality of fourth wiring portions 6d, and a plurality of fifth wiring portions 6e includes first terminal section 63. Second wiring portion 6b is covered with second insulating layer 7. Second wiring layer 8 overlaps second wiring portion 6b. Second wiring layer 8 has an area equal to or larger than that of semiconductor element 1.

Current flowing through semiconductor package 100 according to the first embodiment will now be described.

Semiconductor package 100 according to the present embodiment performs switching operation at large current and high voltage. As shown in FIG. 1, when semiconductor element 1 changes from the on state to the off state in the switching operation, a surge voltage ΔV is applied to semiconductor element 1. Surge voltage ΔV is calculated based on the time rate of change di/dt of current when semiconductor element 1 changes from the on state to the off state, and inductance L of wiring included in semiconductor device 200. Specifically, surge voltage ΔV is expressed by the following equation.

ΔV=L·di/dt

When inductance L and the time rate of change di/dt of current are large, a surge voltage ΔV exceeding the withstand voltage of semiconductor element 1 may occur. This may cause deterioration of semiconductor element 1. It is therefore necessary to reduce the inductance.

The operation effects of the present embodiment will now be described.

In semiconductor package 100 according to the first embodiment, as shown in FIG. 1, second layer section 81 of second wiring layer 8 has a portion overlying first layer section 61 of first wiring layer 6 with second insulating layer 7 interposed. With this configuration, the direction of current flowing through first layer section 61 of first wiring layer 6 can be opposite to the direction of current flowing through the portion of second layer section 81 overlying first layer section 61 of first wiring layer 6 with second insulating layer 7 interposed. Thus, the temporal change of current flowing through first layer section 61 of first wiring layer 6 and the temporal change of current flowing through the portion of second layer section 81 of second wiring layer 8 overlying first layer section 61 with second insulating layer 7 interposed have opposite signs. The magnetic fluxes caused by the time rate of change di/dt of current cancel out. Thus, the wiring inductance due to a commutation loop flowing through first layer section 61 and second layer section 81 can be reduced. In the present embodiment, the commutation loop is current produced when semiconductor element 1 performs switching operation. Accordingly, the inductance of semiconductor package 100 can be reduced.

Since the inductance of semiconductor package 100 can be reduced, occurrence of a surge voltage exceeding the withstand voltage of semiconductor element 1 can be suppressed. Accordingly, deterioration of semiconductor element 1 can be suppressed.

As shown in FIG. 1, first layer section 61 of first wiring layer 6 covers first insulating layer 5. In this configuration, protrusion of first wiring layer 6 along the in-plane direction of first insulating layer 5 can be suppressed. Accordingly, semiconductor package 100 can be reduced in size.

The operation effects of semiconductor package 100 according to the present embodiment will be described in detail in comparison with a semiconductor package 101 according to a first comparative example shown in FIG. 6 and FIG. 7. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 7. As shown in FIG. 6 and FIG. 7, in semiconductor package 101 according to the first comparative example, semiconductor element 1 is connected to an insulating substrate 47 through solder. A lead frame LF is used as a connection terminal to external wiring. Lead frame LF and semiconductor element 1 are connected by, for example, a bonding wire 69. Bonding wire 69 is formed of, for example, copper (Cu) or aluminum (Al). Lead frame LF is typically manufactured by punching a metal plate of copper (Cu), iron (Fe), or the like. Thus, an inner lead IL serving as a bonding section to bonding wire 69 in lead frame LF is arranged on the same plane. Inner lead IL protrudes from the outer periphery of insulating substrate 47. Accordingly, lead frame LF increases the dimension of semiconductor package 100 along the in-plane direction of insulating substrate 47. In comparison, according to the present embodiment, since first layer section 61 of first wiring layer 6 covers first insulating layer 5, semiconductor package 100 can be reduced in size along the in-plane direction of first insulating layer 5.

As shown in FIG. 4 and FIG. 5, first wiring layer 6 and second wiring layer 8 each have an area equal to or larger than that of semiconductor element 1. In this configuration, permissible current (capacity) of first wiring layer 6 and second wiring layer 8 is large. The permissible current of first wiring layer 6 and second wiring layer 8 is larger than, for example, when first wiring layer 6 and second wiring layer 8 are thin lines. Accordingly, large current can be applied to semiconductor element 1 through first wiring layer 6 and second wiring layer 8.

As shown in FIG. 1, organic layer OL overlies second wiring layer 8. This configuration can suppress occurrence of discharge due to foreign substances adhering to second wiring layer 8. Furthermore, when external wiring is bonded to first wiring layer 6 by solder, flowing of the solder on second wiring layer 8 can be suppressed. In other words, organic layer OL can be used as solder resist. Furthermore, for example, compared with when first wiring layer 6, second wiring layer 8, and semiconductor element 1 are arranged in the interior space of a not-shown case and the interior space is sealed by silicone gel or the like, semiconductor package 100 can be insulated while semiconductor package 100 is reduced in size.

As shown in FIG. 1, first wiring portion 6a and second wiring portion 6b are connected by semiconductor element 1, conductive plate 2, and heat spreader 4. With this configuration, even when semiconductor element 1 is a vertical semiconductor element, current can be fed to semiconductor element 1 by first wiring portion 6a and second wiring portion 6b.

As shown in FIG. 1, sealing section 9 seals semiconductor element 1 and conductive plate 2 between first surface 41 and first insulating layer 5. With this configuration, the side surfaces of semiconductor element 1 and conductive plate 2 can be insulated.

As shown in FIG. 1, first insulating layer 5 and second insulating layer 7 are polymer films. With this configuration, the insulation properties of semiconductor package 100 can be enhanced, compared with when an insulating layer of a glass epoxy substrate is used. Furthermore, semiconductor package 100 can be made thin, compared with when an insulating layer of a glass epoxy substrate is used. With this configuration, the thickness of semiconductor package 100 can be reduced. Although not shown in the drawings, for example, even when semiconductor package 100 includes a third insulating film and a third wiring layer, the thickness of semiconductor package 100 can be reduced. Accordingly, semiconductor package 100 can be reduced in size. Furthermore, semiconductor package 100 can be reduced in weight.

Second Embodiment

Referring now to FIG. 8, a configuration of semiconductor package 100 according to a second embodiment will be described. The second embodiment has the same configuration and operation effects as those of the first embodiment unless otherwise specified. Therefore, the same configuration as the foregoing first embodiment is denoted by the same reference sign and a description thereof will not be repeated.

As shown in FIG. 8, in semiconductor package 100 according to the present embodiment, organic layer OL has an organic layer-side through hole OOP. Organic layer-side through hole OOP penetrates organic layer OL. Second terminal section 83 of second wiring layer 8 is arranged inside organic layer-side through hole OOP. Second terminal section 83 is exposed from organic layer-side through hole OOP.

Semiconductor package 100 according to the present embodiment differs from semiconductor package 100 according to the first embodiment in that the location where first wiring layer 6 and second wiring layer 8 are exposed is not on the outer periphery of second insulating layer 7.

The operation effects of the present embodiment will now be described.

In semiconductor package 100 according to the second embodiment, as shown in FIG. 8, second terminal section 83 is exposed from organic layer-side through hole OOP. With this configuration, an external connection terminal can be arranged on the front surface side of organic layer OL. Accordingly, the degree of freedom in design of semiconductor package 100 is improved.

Third Embodiment

Referring now to FIG. 9, a configuration of semiconductor package 100 according to a third embodiment will be described. The third embodiment has the same configuration and operation effects as those of the first embodiment unless otherwise specified. Therefore, the same configuration as the foregoing first embodiment is denoted by the same reference sign and a description thereof will not be repeated.

As shown in FIG. 9, in semiconductor package 100 according to the third embodiment, first insulating layer 5 has a first opening OP1. First opening OP1 penetrates first insulating layer 5. First opening OP1 is spaced apart from semiconductor element 1 and conductive plate 2. Sealing section 9 fills first opening OP1. Thus, sealing section 9 is fitted in first insulating layer 5. Although not shown in the drawing, when a resin adhesive layer is arranged between first insulating layer 5, and semiconductor element 1 and conductive plate 2, first opening OP1 penetrates the resin adhesive layer.

Second insulating layer 7 has a second opening OP2. Second opening OP2 penetrates second insulating layer 7. Second opening OP2 is communicatively connected to first opening OP1. Sealing section 9 fills first opening OP1 and second opening OP2. Thus, sealing section 9 is fitted in first insulating layer 5 and second insulating layer 7. Although not shown in the drawing, when a resin adhesive layer is arranged between second insulating layer 7, and first insulating layer 5 and second wiring layer 8, second opening OP2 penetrates the resin adhesive layer.

The operation effects of the present embodiment will now be described.

In semiconductor package 100 according to the third embodiment, as shown in FIG. 9, sealing section 9 fills first opening OP1. With this configuration, first insulating layer 5 and sealing section 9 can be securely bonded. Accordingly, separation between first insulating layer 5 and sealing section 9 can be suppressed. As shown in FIG. 9, sealing section 9 fills first opening OP1 and second opening OP2. With this configuration, second insulating layer 7 and sealing section 9 can be securely bonded. Accordingly, separation between second insulating layer 7 and sealing section 9 can be suppressed.

Fourth Embodiment

Referring now to FIG. 10, a configuration of semiconductor package 100 according to a fourth embodiment will be described. The fourth embodiment has the same configuration and operation effects as those of the first embodiment unless otherwise specified. Therefore, the same configuration as the foregoing first embodiment is denoted by the same reference sign and a description thereof will not be repeated.

As shown in FIG. 10, semiconductor package 100 according to the fourth embodiment further includes a control board SB and a control component SP. Control board SB is electrically connected to first wiring layer 6. Control component SP includes a first control member SP1 and a second control member SP2. In FIG. 10, control component SP includes two first control members SP1 and a second control member SP2. First control members SP1 are mounted on control board SB. Second control member SP2 is mounted on organic layer OL. Second control member SP2 is electrically connected to second wiring layer 8. Second control member SP2 penetrates organic layer OL and is connected to second wiring layer 8.

Control board SB includes a wiring section SB1, a substrate section SB2, and a connection section SB3. First control member SP1 is electrically connected to wiring section SB1. Wiring section SB1 is electrically connected to first wiring layer 6 by connection section SB3.

The operation effects of the present embodiment will now be described.

In semiconductor package 100 according to the fourth embodiment, as shown in FIG. 10, second control member SP2 of control component SP is mounted on organic layer OL. Second control member SP2 is electrically connected to second wiring layer 8. With this configuration, a part of second wiring layer 8 can be used as a part of a control circuit. Thus, the area of control board SB can be reduced. Accordingly, semiconductor device 200 can be reduced in size.

The operation effects of semiconductor package 100 according to the present embodiment will be described in detail in comparison with a semiconductor package 102 according to a second comparative example shown in FIG. 11. As shown in FIG. 11, in semiconductor package 102 according to the second comparative example, control component SP is mounted on a surface of control board SB. Three first control members SP1 of the control member are mounted on control board SB. Thus, control board SB has an area in which three first control members SP1 can be mounted.

In comparison, in semiconductor package 100 according to the present embodiment, since second control member SP2 is mounted on organic layer OL, control board SB only needs to have an area in which two first control members SP1 can be mounted. Accordingly, the area of control board SB can be reduced.

Fifth Embodiment

Referring now to FIG. 12, a configuration of semiconductor package 100 according to a fifth embodiment will be described. The fifth embodiment has the same configuration and operation effects as those of the first embodiment unless otherwise specified. Therefore, the same configuration as the foregoing first embodiment is denoted by the same reference sign and a description thereof will not be repeated.

As shown in FIG. 12, in semiconductor package 100 according to the fifth embodiment, first wiring layer 6 extends to the outside of the outer periphery of sealing section 9. Specifically, first terminal section 63 of first wiring layer 6 extends to the outside of the outer periphery of sealing section 9. First insulating layer 5 extends to the outside of the outer periphery of sealing section 9. Semiconductor package 100 further includes a connection member CC. Connection member CC is fixed to first insulating layer 5 and first terminal section 63. Connection member CC penetrates first insulating layer 5 and first terminal section 63. Connection member CC is, for example, a bolt and a nut.

The operation effects of the present embodiment will now be described.

In semiconductor package 100 according to the fifth embodiment, as shown in FIG. 12, first wiring layer 6 extends to the outside of the outer periphery of sealing section 9. With this configuration, connection member CC can be fixed to first wiring layer 6. Thus, first wiring layer 6 can be connected to external wiring by connection member CC. Accordingly, semiconductor package 100 can be connected to external wiring more easily than when external wiring is directly connected to first wiring layer 6 or second wiring layer 8 by soldering. Furthermore, semiconductor package 100 can be connected to external wiring more easily than when external wiring is connected to a socket soldered to first wiring layer 6 or second wiring layer 8.

Sixth Embodiment

Referring now to FIG. 13, a configuration of semiconductor package 100 according to a sixth embodiment will be described. The sixth embodiment has the same configuration and operation effects as those of the first embodiment unless otherwise specified. Therefore, the same configuration as the foregoing first embodiment is denoted by the same reference sign and a description thereof will not be repeated.

As shown in FIG. 13, in semiconductor package 100 according to the sixth embodiment, heat spreader 4 includes a first metal plate 46, an insulating substrate 47, and a second metal plate 48. Semiconductor element 1 and conductive plate 2 are electrically connected to first metal plate 46. Insulating substrate 47 is sandwiched between second metal plate 48 and first metal plate 46. Insulating substrate 47 is affixed to first metal plate 46 and second metal plate 48.

The material of first metal plate 46 and second metal plate 48 is, for example, a metal having high conductivity, such as copper (Cu) and aluminum (Al). Insulating substrate 47 is, for example, a ceramic plate. Insulating substrate 47 has a higher thermal conductivity than a resin insulating layer RL described later (see FIG. 14). The operation effects of the present embodiment will now be described.

In semiconductor package 100 according to the sixth embodiment, as shown in FIG. 13, the insulating plate is sandwiched between second metal plate 48 and first metal plate 46. In this configuration, first metal plate 46 and second metal plate 48 are insulated by insulating substrate 47. Thus, when a heat sink HS described later (see FIG. 14) is bonded to semiconductor package 100, semiconductor element 1 and heat sink HS (see FIG. 14) can be insulated by insulating substrate 47. Thus, it is not necessary to arrange an insulating layer between heat spreader 4 and heat sink HS (see FIG. 14). Furthermore, second metal plate 48 of heat spreader 4 and heat sink HS (see FIG. 14) can be bonded, for example, by solder having a high thermal conductivity. Accordingly, the heat dissipation of semiconductor package 100 is improved.

Seventh Embodiment

Referring now to FIG. 14, a configuration of semiconductor package 100 and a semiconductor device 200 according to a seventh embodiment will be described. The seventh embodiment has the same configuration and operation effects as those of the fourth embodiment unless otherwise specified. Therefore, the same configuration as the foregoing fourth embodiment is denoted by the same reference sign and a description thereof will not be repeated.

As shown in FIG. 14, semiconductor device 200 according to the seventh embodiment includes semiconductor package 100 described in the first to sixth embodiments, a heat sink HS, and a resin insulating layer RL. Resin insulating layer RL is sandwiched between heat sink HS and heat spreader 4. Thus, the semiconductor package is bonded to heat sink HS by resin insulating layer RL. In FIG. 14, semiconductor device 200 includes semiconductor package 100 described in the fourth embodiment. Semiconductor package 100 is attached to heat sink HS by resin insulating layer RL. Semiconductor package 100 is insulated from heat sink HS by resin insulating layer RL.

Heat sink HS includes a base HS1 and a plurality of fins HS2. Base HS1 is bonded to heat spreader 4. Base HS1 is sandwiched between a plurality of fins HS2 and heat spreader 4.

Referring now to FIG. 14 to FIG. 16, a method of manufacturing semiconductor device 200 according to the seventh embodiment will be described.

As shown in FIG. 15, first insulating layer 5 is arranged so as to cover semiconductor element 1 and conductive plate 2, and then first wiring layer 6, second insulating layer 7, second wiring layer 8, and organic layer OL are overlaid. Subsequently, as shown in FIG. 16, semiconductor element 1 and conductive plate 2 are bonded to heat spreader 4 by bonding material 3. Subsequently, as shown in FIG. 14, semiconductor element 1, conductive plate 2, and heat spreader 4 are sealed by sealing section 9, and then heat spreader 4 is attached to heat sink HS by resin insulating layer RL.

The operation effects of the present embodiment will now be described.

In semiconductor device 200 according to the seventh embodiment, as shown in FIG. 14, resin insulating layer RL is sandwiched between heat sink HS and heat spreader 4. With this configuration, heat produced from semiconductor element 1 of semiconductor package 100 is transmitted to heat sink HS through heat spreader 4 and resin insulating layer RL. Thus, heat produced from semiconductor element 1 is dissipated from heat sink HS. Accordingly, the heat dissipation of semiconductor device 200 is improved.

Eighth Embodiment

Referring now to FIG. 17, a configuration of semiconductor device 200 according to an eighth embodiment will be described. The eighth embodiment has the same configuration and operation effects as those of the sixth embodiment unless otherwise specified. Therefore, the same configuration as the foregoing sixth embodiment is denoted by the same reference sign and a description thereof will not be repeated.

As shown in FIG. 17, semiconductor device 200 according to the eighth embodiment includes semiconductor package 100 described in the sixth embodiment, heat sink HS, and a conductive metal bonding material ML. Conductive metal bonding material ML is sandwiched between heat sink HS and second metal plate 48 of heat spreader 4. Thus, semiconductor package 100 is bonded to heat sink HS by conductive metal bonding material ML. Conductive metal bonding material ML includes, for example, solder, silver (Ag), and copper (Cu). Conductive metal bonding material ML has conductivity. Conductive metal bonding material ML has a higher electrical conductivity than resin insulating layer RL (see