310 and the second semiconductor chip 320 may be mounted on the upper side of the interposer structure 200. For example, a third connecting member 352 may be formed between the interposer structure 200 and the first semiconductor chip 310. The third connecting member 352 may connect a part of the plurality of second interposer pads 204 to the first chip pad 312. Accordingly, the interposer structure 200 and the first semiconductor chip 310 may be electrically connected.

Further, for example, a fourth connecting member 354 may be formed between the interposer structure 200 and the second semiconductor chip 320. The fourth connecting member 354 may connect the other part of the plurality of second interposer pads 204 to the second chip pad 314. Accordingly, the interposer structure 200 and the second semiconductor chip 320 may be electrically connected.

In some example embodiments, the size of the third connecting member 352 may be smaller than the sizes of the first connecting member 150 and the second connecting member 250. For example, a width W3 of the third connecting member 352 in the first direction X is smaller than a width W1 of the first connecting member 150 in the first direction X. The width W3 of the third connecting member 352 in the first direction X is smaller than the width W2 of the second connecting member 250 in the first direction X. The volume of the third connecting member 352 may be smaller than the volume of the first connecting member 150 and the volume of the second connecting member 250.

In some example embodiments, the size of the fourth connecting member 354 may be smaller than the size of the first connecting member 150 and the second connecting member 250. For example, the width W4 of the fourth connecting member 354 in the first direction X is smaller than the width W1 of the first connecting member 150 in the first direction X. The width W3 of the fourth connecting member 354 in the first direction X is smaller than the width W2 of the second connecting member 250 in the first direction X. The volume of the fourth connecting member 354 may be smaller than the volume of the first connecting member 150 and the volume of the second connecting member 250.

The third connecting member 352 and the fourth connecting member 354 may each be, but are not limited to, a solder bump including a low-melting point metal, for example, tin (Sn), tin (Sn) alloy, or the like. The third connecting member 352 and the fourth connecting member 354 may have various shapes such as a land, a ball, a pin, and a pillar, respectively. Further, the third connecting member 352 and the fourth connecting member 354 may each include a UBM (Under Bump Metallurgy).

The third connecting member 352 and the fourth connecting member 354 may be formed of a single layer or multiple layers, respectively. When the third connecting member 352 and the fourth connecting member 354 are each formed of a single layer, the third connecting member 352 and the fourth connecting member 354 may each include tin-silver (Sn—Ag) solder or copper (Cu) as an example. When the third connecting member 352 and the fourth connecting member 354 are each formed of multiple layers, the third connecting member 352 and the fourth connecting member 354 may each include copper (Cu) pillar and solder as an example. However, the example embodiments are not limited thereto, and the number, spacing, placement, form, and the like of each of the third connecting member 352 and the fourth connecting member 354 are not limited to those shown in the drawings, and may vary depending on the design.

In some example embodiments, a part of the redistribution layer 240 may electrically connect the third connecting member 352 and the fourth connecting member 354. For example, a part of the redistribution layer 240 may be connected to the second interposer pad 204 connected to the third connecting member 352, and may be connected to the second interposer pad 204 connected to the fourth connecting member 354. Accordingly, the first semiconductor chip 310 and the second semiconductor chip 320 may be electrically connected.

In some example embodiments, a second underfill 362 may be formed between the interposer structure 200 and the first semiconductor chip 310. A third underfill 364 may be formed between the interposer structure 200 and the second semiconductor chip 320. The second underfill 362 may fill the space between the interposer structure 200 and the first semiconductor chip 310. The third underfill 364 may fill the space between the interposer structure 200 and the second semiconductor chip 320. Further, the second underfill 362 may cover the third connecting member 352. The third underfill 364 may cover the fourth connecting member 354.

The second underfill 362 and the third underfill 364 may inhibit or prevent breakage or the like of the first and second semiconductor chips 310 and 320, by fixing the first and second semiconductor chips 310 and 320 onto the interposer structure 200. The second underfill 362 and the third underfill 364 may each, include, but are not limited to, insulating polymer materials such as EMC.

The mold layer 400 may be placed on the interposer structure 200. The mold layer 400 may be provided between the first semiconductor chip 310 and the second semiconductor chip 320. The mold layer 400 may separate the first semiconductor chip 310 and the second semiconductor chip 320 from each other.

In some example embodiments, the mold layer 400 may include a first trench TR1 and a second trench TR2. The first semiconductor chip 310 may be mounted inside the first trench TR1. The second semiconductor chip 320 may be mounted inside the second trench TR2. Although each of one first trench TR1 and one second trench TR2 is shown. In FIGS. 1 and 2, the example embodiments are not limited thereto. At least one or more first trenches TR1 and second trenches TR2 may be provided.

The mold layer 400 may include, for example, but is not limited to, an insulating polymer material such as EMC. The mold layer 400 may include a material different from the first underfill 260, the second underfill 362, and the third underfill 364. For example, the first underfill 260, the second underfill 362, and the third underfill 364 may each include an insulating material having a higher fluidity than the mold layer 400. Therefore, the first underfill 260, the second underfill 362, and the third underfill 364 may efficiently fill a narrow space between the circuit board 100 and the interposer structure 200, or between the interposer structure 200 and the first and second semiconductor chips 310 and 320.

FIG. 3 is an enlarged view of a region P of FIG. 2. A mold layer 400 according to some example embodiments will be described in more detail using FIG. 3.

Referring to FIG. 3, the mold layer 400 may include a pair of side walls 400SW, a bottom side 400BS, and an upper side 400US.

The upper side 400US of the mold layer 400 may come into contact with an adhesive layer 500. The upper side 400US of the mold layer 400 may be opposite to the interposer structure 200. The bottom side 400BS of the mold layer 400 may come into contact with the interposer structure 200. The upper side 400US of the mold layer 400 and the bottom side 400BS of the mold layer 400 may be opposite to each other. The side walls 400SW of the mold layer 400 may be connected to the upper side 400US of the mold layer 400, and may be connected to the bottom side 400BS of the mold layer 400.

In some example embodiments, the upper side 400US of the mold layer 400 may be placed on the same plane as the upper side 310US of the first semiconductor chip 310 and the upper side 320US of the second semiconductor chip 320. That is, a height in the third direction Z from the upper side of the interposer structure 200 to the upper side 400US of the mold layer 400 may be the same as the height in the third direction Z from the upper side of the interposer structure 200 to the upper side 310US of the first semiconductor chip 310, and the height from the upper side of the interposer structure 200 to the upper side 320US of the second semiconductor chip 320.

In some example embodiments, a slope of the side wall 400SW of the mold layer 400 may be constant as it goes away from the upper side of the interposer structure 200. That is, the side walls 400SW of the mold layer 400 may be a straight line. A first angle θ1 formed by the bottom side 400BS of the mold layer 400 and the side wall 400SW of the mold layer 400 may be 90° or less. As an example, the first angle θ1 formed by the bottom side 400BS of the mold layer 400 and the side wall 400SW of the mold layer 400 may be 90°.

That is, the side walls 400SW of the mold layer 400 may extend in the third direction Z. The mold layer 400 may be formed by first forming a pre-mold layer (e.g., 400p of FIG. 15) on the interposer structure 200 and etching the pre-mold layer (e.g., 400p of FIG. 15). The pre-mold layer (e.g., 400p of FIG. 15) may be isotropically etched in the third direction Z. Therefore, the side walls 400SW of the mold layer 400 may be a straight line.

In some example embodiments, a second angle θ2 formed by the bottom side TR1_BS of the first trench TR1 and the side wall TR1_SW of the first trench TR1 may be 90° or more. As an example, the second angle θ2 formed by the bottom side TR1_BS of the first trench TR1 and the side wall TR1_SW of the first trench TR1 may be 90°. A third angle θ3 formed by the bottom side TR2_BS of the second trench TR2 and the side wall TR2_SW of the second trench TR2 may be 90° or more. As an example, the third angle θ2 formed by the bottom side TR2_BS of the second trench TR2 and the side wall TR2_SW of the second trench TR2 may be 90°.

In some example embodiments, a contact surface on which the second underfill 362 and the mold layer 400 come into contact with each other may be a straight line. A contact surface on which the third underfill 364 and the mold layer 400 come into contact with each other may be a straight line. The side walls of the second underfill 362 and the side walls of the third underfill 364 may each be a straight line. For example, the slope of the side wall of the second underfill 362 may be constant as it goes away from the upper side of the interposer structure 200. The slope of the side wall of the third underfill 364 may be constant as it goes away from the upper side of the interposer structure 200. The angle formed by the side wall and the bottom side of the second underfill 362 may be 90° or more. The angle formed by the side wall and the bottom side of the third underfill 364 may be 90° or more. However, the example embodiments are not limited thereto.

Referring to FIG. 2 again, the semiconductor package according to some example embodiments may further include an adhesive layer 500 and a heat slug 600.

The adhesive layer 500 may be provided on the mold layer 400. The adhesive layer 500 may be provided on the first semiconductor chip 310 and the second semiconductor chip 320. The adhesive layer 500 may come into contact with the upper side 400US of the mold layer 400. The adhesive layer 500 may come into contact with the upper side 310US of the first semiconductor chip 310 and the upper side 320US of the second semiconductor chip 320. The adhesive layer 500 may bond and fix the mold layer 400, the first semiconductor chip 310, the second semiconductor chip 320, and the heat slug 600 to each other. The adhesive layer 500 may include an adhesive material. For example, the adhesive layer 500 may include a curable polymer. The adhesive layer 500 may include, for example, an epoxy-based polymer.

The heat slug 600 may be placed on the circuit board 100. The heat slug 600 may cover the first semiconductor chip 310 and the second semiconductor chip 320. The heat slug 600 may include, but is not limited to, a metal material.

FIG. 4 is an example diagram for explaining a semiconductor package according to some example embodiments. For convenience of explanation, repeated contents of those explained using FIGS. 1 to 3 will be omitted.

Referring to FIG. 4, the mold layer 400 may completely cover the first semiconductor chip 310 and the second semiconductor chip 320.

A height in the third direction Z from the upper side of the interposer structure 200 to the upper side 400US of the mold layer 400 is greater than a height in the third direction Z from the upper side of the interposer structure 200 to the upper side 310US of the first semiconductor chip 310. The height in the third direction Z from the upper side of the interposer structure 200 to the upper side 400US of the mold layer 400 is greater than the height in the third direction Z from the upper side of the interposer structure 200 to the upper side 320US of the second semiconductor chip 320.

The adhesive layer 500 may adhere better to the mold layer 400 than the first and second semiconductor chips 310 and 320. As the area of the mold layer 400 coming into contact with the adhesive layer 500 is increased, a semiconductor package having high stability may be provided.

FIG. 5 is an example diagram for explaining a semiconductor package according to some example embodiments. FIG. 6 is an enlarged view of a region Q of FIG. 5. For convenience of explanation, repeated contents of those explained using FIGS. 1 to 3 will be omitted.

Referring to FIGS. 5 and 6, the semiconductor package according to some example embodiments may include an air gap 405. An angle formed by the side walls 400SW of the mold layer 400 and the bottom side 400BS of the mold layer 400 may be smaller than 90°.

In the process of etching the pre-mold layer (e.g., 400p of FIG. 15) to form the mold layer 400, the width of the first trench TR1 in the first direction X or the second direction Y may gradually decrease from the upper side of the pre-mold layer (e.g., 400p of FIG. 15) toward the interposer structure 200. That is, the side wall 400SW of the mold layer 400 may extend in a direction different from the third direction Z. The side wall 400SW of the mold layer 400 may extend in an arbitrary direction between the first direction X and the third direction Z.

In some example embodiments, the first angle θ1 formed by the side wall 400SW of the mold layer 400 and the bottom side 400BS of the mold layer 400 is smaller than 90°. The second angle θ2 formed by the side wall TR1_SW of the first trench TR1 and the bottom side TR1_BS of the first trench TR1 is greater than 90°. The third angle θ3 formed by the side wall TR2_SW of the second trench TR2 and the bottom side TR2_BS of the second trench TR2 is greater than 90°.

The air gap 405 may be placed between the mold layer 400 and the first semiconductor chip 310, or between the mold layer 400 and the second semiconductor chip 320. As a structure is provided in which the width of the first trench TR1 and the width of the second trench TR2 gradually decrease toward the interposer structure 200, and the width of the first semiconductor chip 310 and the width of the second semiconductor chip 320 are constant, the air gap 405 may be formed between the first semiconductor chip 310 and the mold layer 400, and between the second semiconductor chip 320 and the mold layer 400. In contrast, other materials may be filled between the first semiconductor chip 310 and the mold layer 400, and between the second semiconductor chip 320 and the mold layer 400.

FIGS. 7 to 12 are example diagrams for explaining a semiconductor package according to some example embodiments. For convenience of explanation, points different from those described using FIGS. 1 to 3 will be mainly described. For reference, FIGS. 7 to 12 may be example plan views of the semiconductor package according to some example embodiments.

First, referring to FIG. 7, a semiconductor package according to some example embodiments may include one first semiconductor chip 310 and two second semiconductor chips 320. In some example embodiments, the first semiconductor chip 310 may be a logic chip, and the second semiconductor chip 320 may be a memory chip. That is, in some example embodiments, one logic chip and a plurality of memory chips may be mounted on one interposer structure 200.

The first semiconductor chip 310 may be spaced apart from the second semiconductor chips 320 in the first direction X. The second semiconductor chips 320 may be spaced apart from each other in the second direction Y. In some example embodiments, the ratio of the first semiconductor chip 310 to the second semiconductor chip 320 may be, but is not limited to, 1:2 (e.g., one first semiconductor chip 310 for every two second semiconductor chips 320).

In some example embodiments, the area of the cross section of the first trench TR1 may be greater than the area of the cross section of the second trench TR2 from a planar viewpoint. The size of the first semiconductor chip 310 may be larger than the size of the second semiconductor chip 320. However, the example embodiments are not limited thereto.

Referring to FIG. 8, the semiconductor package according to some example embodiments may include one first semiconductor chip 310 and four second semiconductor chips 320. That is, one logic chip and four memory chips may be mounted on one interposer structure 200.

The first semiconductor chip 310 may be provided between the second semiconductor chips 320. The second semiconductor chip 320 may be provided around the first semiconductor chip 310. The second semiconductor chip 320 may have a structure that surrounds the first semiconductor chip 310 from a planar viewpoint.

In some example embodiments, the area of the cross section of the first trench TR1 may be greater than the area of the cross section of the second trench TR2 from a planar viewpoint. The size of the first semiconductor chip 310 may be greater than the size of the second semiconductor chip 320. However, the example embodiments are not limited thereto.

Referring to FIG. 9, the semiconductor package according to some example embodiments may include two first semiconductor chips 310 and eight second semiconductor chips 320. That is, two logic chips and eight memory chips may be mounted on one interposer structure 200.

The first semiconductor chips 310 may be spaced apart from each other in the second direction Y. The second semiconductor chips 320 may be aligned with each other in the second direction Y. The second semiconductor chip 320 may be spaced apart from each other in the first direction X and the second direction Y. The first semiconductor chip 310 may be provided between the second semiconductor chips 320. In some example embodiments, the ratio of the first semiconductor chip 310 to the second semiconductor chip 320 may be, but not limited to, 2:8.

Referring to FIGS. 10 to 12, the shapes of the first trench TR1 and the second trench TR2 may be one of a circle, a hexagon or an octagon from a planar viewpoint.

The mold layer 400 may be formed by etching the pre-mold layer (