416 may have a feature pitch ranging from 100 nm to several microns, for example.

In the illustrated example, each IC die 415 further includes one or more through die substrate vias (TSVs) 418 extending from die backside surface 214 through IC die substrate material 417. IC die TSVs 418 couple with IC layer 416, for example contacting one or more metallization features and/or terminals of active or passive devices. IC die TSVs 418 may have any architecture and generally include a metallization, such as, but not limited to, Cu.

Each of IC dies 415 may therefore be a fully functional ASIC, or may be a chiplet or tile that has more limited functionality supplementing the function of one or more other IC dies that are to be part of the same multi-chip device. A chiplet or tile may, for example, be any of a wireless radio circuit, microprocessor core, electronic memory circuit, floating point gate array (FPGA), power management and/or power supply circuit, or include a MEMS device. In some examples, one or more of IC dies 415 include one or more banks of active repeater circuitry to improve multi-chip interconnects (e.g., network-on-chip architectures). In other examples, one or more of IC dies 415 includes clock generator circuitry or temperature sensing circuitry. In other examples, one or more of IC dies 415 include logic circuitry that, along with other IC dies 415 implement 3D logic circuitry (e.g., mesh network-on-chip architectures). In still other examples, at least one of IC dies 415 includes microprocessor core circuitry, for example comprising one or more shift registers. In another example, at least one of IC die 415 is a photonic IC (PIC), for example comprising one or more optical waveguides, optical multiplexer/demultiplexer, lasers and/or photodetectors. For some such embodiments, the glass substrate 212 conveys optical signals to/from IC die 415 with optical waveguide 216.

FIG. 5 further illustrates workpiece 200 after application of a filler 520 followed by planarization of the front-side surface of workpiece 200. As shown, filler 520 may be retained within the gap between die edge sidewall 419 and glass sidewall 422 while any overburden may be removed during planarization. An amount of filler 520 may also be retained over a surface of thin IC die that are recessed well below glass substrate 212.

For the illustrated embodiment where IC die 415 are “front-side up,” planarization may stop upon exposing an uppermost one of IC layers 416. For alternative embodiments where IC die 415 are “front-side down,” planarization may remove any amount of IC die substrate material 417 desired, for example to planarize IC die of different thickness, etc. The planarization process may also reduce the thickness of glass substrate 212 to a final thickness T2 that is substantially equal to a thickness of at least one of the IC dies 415.

Filler 520 may have any composition and may be applied to workpiece 200 according to any technique suitable for the material. Filler 520 is advantageously an electrical insulator. In some examples, filler 520 is an organic dielectric, for example comprising an epoxy or polyimide. The organic dielectric may be applied, for example, with a molding process. In other embodiments, filler 520 is an inorganic dielectric material and may have composition known to be suitable as an insulator of monolithic integrated circuitry, such as, but not limited to, silicon dioxide, silicon nitride, silicon oxynitride, or a low-k material having a relative permittivity below 3.5. Inorganic dielectric materials may be deposited with any techniques known to be suitable, such as, but not limited to chemical vapor deposition (CVD).

For embodiments where a thin IC die 415 is recessed within a cavity that does not extend through the glass substrate thickness T2, addition TGVs 525 may extend through any partial thickness of glass substrate 212 to reveal interconnect features on the thin IC die 415. TGVs 525 may also have any architecture and generally include a metallization, such as, but not limited to, Cu. TGVs 525 may also be fabricated as part of methods 101 (FIG. 1) or may be prefabricated in the glass substrate received as an input to methods 101. TGVs 525 may be formed, for example, with a milling, ablation, or etching process similar to any that may be enlisted to form the IC die cavities within glass substrate 212. Metallization may be then deposited in the through via openings, for example with a plating process.

Returning to FIG. 1, methods 101 continue at block 135 where an interconnect bridge die is attached to the IC dies. The interconnect bridge die includes interconnect metallization, for example that has been fabricated with a back-end-of-line (BEOL) monolithic manufacturing process. The interconnect bridge die may be attached at block 135 according to any techniques for die-to-die coupling know to be suitable for IC die stack, for example. In some exemplary embodiments, the interconnect bridge die is directly bonded, for example to with a hybrid bonding process, to interconnect features on a surface of each of multiple IC dies assembled at block 130. In some other embodiments, the interconnect bridge die is indirectly bonded, for example with a solder bonding process, to interconnect features on a surface of each of multiple IC dies assembled at block 130.

In the example illustrated in FIG. 6A, an interconnect bridge die 615 has been directly bonded to surfaces of IC die 415. In some exemplary embodiments, bridge die 615 is a “passive” die and lacks any FETs fabricated within IC layer 416. Such passive die may merely include interconnect routing level, for example resulting from any backend of line monolithic die fabrication process. In addition to in bridge die 615 may include devices such as resistors, capacitors, or inductors (not depicted). Bridge die 615 may have edge length to overlap a portion of two or more IC dies 415. Bridge die 615 therefore spans a length L of glass substrate 212 between two laterally adjacent IC dies 415. In some exemplary hybrid bonding embodiments, bridge die 615 is in direct contact with glass substrate 212. Bridge die 615 may only be large enough to overlap a portion of two adjacent IC dies 415, or may be larger so as to extend any lateral distance past edge sidewalls of one or more IC dies 415.

For some embodiments illustrated in FIG. 6A where bridge die 615 is face-to-face with IC dies 415, metallization features within IC layers 416 of bridge die 615 are directly coupled with metallization features within IC layers 416 of two or more IC dies 415. For other embodiments further illustrated in FIG. 6A where bridge die 615 is face-to-back with IC dies 415, metallization features within IC layers 416 of bridge die 615 are directly coupled with TSVs 418 two or more IC dies 415. FIG. 6A further illustrates another embodiment where bridge die 615 is face-to-back with one IC die 415 and face-to-face with another IC die 415.

For hybrid bonded embodiments, metal features of bridge die 615 are fused to those of the IC die 415, the resulting composite, quasi-monolithic structure may comprise a hybrid bonded interface of both metallurgically interdiffused metals and chemically bonded insulators.

Hybrid bonding surfaces of IC dies 415 are substantially co-planar. Bridge die 615 may be aligned to a target location on each of IC dies 415 with any high-resolution alignment tool, for example of the type found on a chip-level bonding tool commercially available through a number of industry suppliers. Direct bonding of bridge die 615 to IC dies 415 may sinter metallization features (e.g., via metal interdiffusion) and also bond dielectric materials (e.g., via Si—O—Si condensation bonds). Any direct bonding technique(s) suitable for the IC die and host substrate may be practiced. Thermo-compression bonding may be at low temperature (e.g., below melting temperature of the interconnects, and more specifically below 100° C.). Direct bonding at room temperature (i.e., compression only) is also possible. Prior to bonding, any of bridge die 615 or IC dies 415 may be pre-processed, for example with a plasma clean, to activate their surfaces for the bonding. Post bonding, selective heating may be performed to make permanent the bond (e.g., by converting a van der waals bond into a sintered Cu—Cu bond through interdiffusion). For selective heating, a laser may be employed to limit heating to a specific one IC die 415 and/or bridge die 615.

Lateral (e.g., x-axis) misalignment or misregistration between conductive features of bridge die 615 and IC dies 415 may be less than 0.2 μm. However, lateral misalignment between one conductive feature (e.g., a line or trace) and another conductive feature (e.g., a via) within a monolithic IC die may be at least an order of magnitude smaller than the lateral misalignment between bonded conductive features. The lateral dimensions of metallization features at the bond interface are therefore sufficiently large to accommodate such lateral offset.

For solder bonded embodiments, metal features of bridge die 615 are coupled to those of the IC die 415 with an intervening solder feature (not depicted). Such solder features may comprise any solder alloy (e.g., SAC) as embodiments are not limited in this respect.

In the example illustrated in FIG. 6A, following die attached, bridge die 615 is encapsulated in package dielectric material 618. Package dielectric material 618 may be overmolded around bridge die 615, for example. In some embodiments, an epoxy resin is applied with a molding process to encapsulate bridge die 615. The mold material may be applied to fully encapsulate sidewalls and back-side surface of bridge die 615. Upon curing, package dielectric material 618 may support workpiece 200, enabling carrier 201 to then be removed to expose an opposite side of IC dies 415. For embodiments where bridge die 615 is soldered to IC die 415, an underfill material (not depicted) may present between the solder features.

FIG. 6B illustrates an alternative embodiment where bridge die 615 is embedded within a glass substrate 612. For such embodiments, bridge die 615 may have been assembled into glass substrate 612 substantially as described above for IC dies 415. Accordingly, glass substrate 612 may have any of the properties described above for glass substrate 212. A filler 620 between edges of bridge die 615 and glass substrate 612 may similarly have any of the properties described above for filler 520. In some embodiments, glass substrate 612 is substantially the same as glass substrate 212. For hybrid bonding embodiments, in addition to bridge die 615 being directly bonded to IC dies 415, glass substrate 612 may be directly bonded to glass substrate 212. Although embodiments including glass substrate 612 are well suited to hybrid bonding, solder bonding is also possible in which case an underfill (not depicted) may be present between the solder features and within any gap between glass substrates 212 and 612, as stood off by the solder features.

Notably, the treatment of the IC die and bridge die may be exchanged between blocks 130 and 135 (FIG. 1). For example, at block 130 a bridge die may be embedded within a cavity of a glass substrate at block 130 (substantially as illustrated in FIG. 6B). IC die to be interconnected by the bridge die may be attached at block 135 in substantially the same manners as described above (e.g., direct bonding or solder bonding). Where both the bridge die and the IC die are embedded within a glass substrate, the resulting multi-chip devices will be substantially the same regardless of whether the IC die or a bridge die initiated the “die-first” methods 101. For other embodiments, where only the die that initiate the “die-first” methods 101 is embedded in a glass substrate, the location of the glass substrate within a multi-chip device is indicative of which of the IC die or bridge die was processed at block 130.

Methods 101 continue at block 140 where package dielectric(s) and redistribution layer (RDL) features are formed on a second (opposite) side of the work piece following carrier removal. Formation of RDL features at block 140 is optional and need not be performed for embodiments where the second side of a glass substrate is merely to be directly bonded or soldered to a substrate package. Regardless, when the carrier is removed, an additional (e.g., backside) planarization process may be performed for embodiments where removal of the carrier does not also expose the IC dies. For example, where the IC die cavities do not extend through the entire thickness of the glass substrate, a portion of the glass substrate underlying the IC die may be removed with a planarization process (e.g., grind or polish) to expose a second side of the IC die. In other examples, even where the IC die cavities do extend through the entire thickness of the glass-section substrate, a back side of the glass substrate may be planarized along with any bond/adhesion material that adhered the IC die within the glass cavity.

In exemplary embodiments, the RDL features formed at block 140 comprise metallization features fanning out I/O from the IC dies to interconnect interfaces that are to interconnect to a host of the multi-chip device. The number of layers and/or thicknesses of RDL metallization may vary according to implementation and needs of the particular IC die.

In the example shown in FIG. 7, carrier 201 has been removed from workpiece 200 and optional electrically conductive through-glass vias (TGVs) 724 formed through the entire glass thickness T2. For some embodiments illustrated in FIG. 7 where a thin IC die 415 is recessed within a cavity that does not extend through the glass thickness T2, TGVs 724 may also be formed through any partial thickness of glass substrate 212 to reveal interconnect features on the thin IC die 415. TGVs 724 may have any architecture and generally include a metallization, such as, but not limited to, Cu. TGVs 724 may be fabricated as part of methods 101 (FIG. 1), for example after carrier removal as illustrated. Alternatively, TGVs 724 may be prefabricated in a glass substrate received as an input to methods 101. Regardless, TGVs 724 may be formed, for example, with a milling, ablation, or etching process similar to any that may be enlisted to form the IC die cavities within glass substrate 212. Metallization may be then deposited in the through via openings, for example with a plating process.

FIG. 8 illustrates workpiece 200 evolving to further include a first package dielectric 828 formed in contact with both a second side of the IC dies 415 and in contact with a second side of glass substrate 212. In exemplary embodiments, package dielectric 828 is an organic material, such as, an epoxy resin, phenolic-glass, or a resinous film such as the GX-series films commercially available from Ajinomoto Fine-Techno Co., Inc. (ABF). Package dielectric 828 may comprise epoxy resins (e.g., an acrylate of novolac such as epoxy phenol novolacs (EPN) or epoxy cresol novolacs (ECN)). In some specific examples, package dielectric 828 is a bisphenol-A epoxy resin, for example including epichlorohydrin. In other examples, package dielectric 828 includes bisphenol-F epoxy resin (with epichlorohydrin). In other examples, package dielectric 828 includes aliphatic epoxy resin, which may be monofunctional (e.g., dodecanol glycidyl ether), difunctional (butanediol diglycidyl ether), or have higher functionality (e.g., trimethylolpropane triglycidyl ether). In still other examples, package dielectric 828 includes glycidylamine epoxy resin, such as triglycidyl-p-aminophenol (functionality 3) and N,N,N′,N′-tetraglycidyl-bis-(4-aminophenyl)-methane (functionality 4). Depending on the embodiment, package dielectric 828 may be any of a molding compound, a spin-on material, or dry film laminate material, for example. Package dielectric 828 may be introduced wet/uncured into a cast and then dried/cured. Alternatively, package dielectric 828 may be introduced as a semi-cured dry film that is fully cured followings its application to workpiece 200.

As further illustrated in FIG. 8, openings 816 may be formed through package dielectric 828 to expose metallization features of either an uppermost one of metallization layer within device layers 416 or to expose TSVs 418, depending on the orientation IC dies 415 were assembled into glass substrate 212. Openings 816 may also expose TGVs 724. Any technique suitable for the composition of package dielectric 828 may be employed to form openings 816. For embodiments where package dielectric 828 is photosensitive, a lithographic process may directly pattern package dielectric 828. Alternatively, a photolithographic masking process may be performed and package dielectric 828 etched according to the mask. In other embodiments, openings 816 may be ablated, for example with a laser.

FIG. 9 further illustrates a complete package routing structure 940 built-up workpiece 200. Package routing structure 940 comprises RDL metallization features 920 that backfill openings in one or more layers of package dielectric 828. There may be any number of RDL metallization features 920 built up on a second side of workpiece 200. In the embodiment illustrated, RDL metallization features 940 terminate with first-level interconnect interfaces 922. RDL metallization features 920 may therefore be built up on a backside or frontside of IC dies 415 depending on which side of the IC dies 415 is coupled to bridge die 615. In the example illustrated in FIG. 9, interconnect interfaces 922 are pillars or pads surrounded by a solder resist 923. Hence, in accordance with the illustrated embodiment, routing structure 940 fan-outs interconnections of the multiple IC dies 415 for further coupling with an external host (not depicted). Routing structure 940 may also be further coupled to bridge die 615, for example through TGVs 724, Accordingly, interconnection between IC dies 415 need not be exclusively through bridge die 615.

Conductive RDL metallization features 920 may be formed with an additive or semi-additive process, for example. In some embodiments, each layer of RDL metallization features 920 are formed by first depositing a seed layer (e.g., Cu) and then forming a plating resist mask (not depicted) over the seed layer. With an electrolytic deposition process, Cu is plated upon the seed layer wherever the resist mask is absent. Accordingly, RDL metallization features 920 may have substantially the same composition (e.g., predominantly Cu). The building up of RDL metallization features 920 may comprise any number of cycles with each cycle including package dielectric application, patterning of the package dielectric, and plating of conductive features upon the patterned package dielectric.

Although FIG. 7-9 are illustrated in the context of workpiece 200 evolving from the embodiment illustrated in FIG. 6B, workpiece 200 may instead evolve from the embodiment illustrated in FIG. 6A in substantially the same manner as illustrated in FIG. 7-9 with only a difference in the material surrounding edges of bridge die 615.

Returning to FIG. 1, methods 101 end with the completion of the multi-chip device package structures. In accordance with some embodiments, first level interconnects (FLI) may be formed on exposed surfaces of conductive features of the package structures in preparation for packaging or assembly. In exemplary embodiments, solder features are formed as the FLI. The multi-chip device package structures may then be singulated according to any techniques known to be suitable for glass substrates. Multi-chip device structures may be separated by kerf or panel frame with each multi-chip device including at least two IC dies that are interconnected to each other through a bridge die attached to a side of the IC dies opposite the first-level interconnect interfaces.

FIG. 10 illustrates a system including multi-chip device structure 1000 attached to a host component 1005 by reflowing FLI interconnects 1011. In exemplary embodiments, FLI interconnects 1011 are solder (e.g., SAC) microbumps although other interconnect features are also possible. Host component 1005 may also comprise one or more materials known to be suitable as interposers or package substrates (e.g., an epoxy preform, cored or coreless laminate board, etc.). Host component 1005 may include one or more metallized redistribution levels (not depicted) embedded within a dielectric material. Host component 1005 may also include one or more IC die embedded therein.

Host component 1005 may further include second level interconnects (SLI) 1020. SLI 1020 may comprise any solder (ball, bump, etc.) suitable for a given host board architecture (e.g., surface mount FR4, etc.). As illustrated in dashed line, one or more heat spreaders and/or heat sinks 1050 may be further coupled to multi-chip device 900, which may be advantageous, for example, where IC dies 415 comprise one or more CPU cores or other circuitry of similar power density.

FIG. 11 illustrates a mobile computing platform 1105 and a data server machine 1106 employing a multi-chip IC device with die embedded in a glass substrate and interconnected with a bridge die on one side and redistribution layer metallization features on the opposite side, for example as described elsewhere herein. Server machine 1106 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes multichip device 900, for example as described elsewhere herein. The mobile computing platform 1105 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1105 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), an integrated system 1110, and a battery 1115.

As illustrated in the expanded view, multi-chip device 900 is coupled to one or more of a power management integrated circuit (PMIC) or RF (wireless) integrated circuit (RFIC) including a wideband RF (wireless) transmitter and/or receiver. A PMIC may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 1115 and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, an RFIC has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, and beyond.

FIG. 12 is a block diagram of a cryogenically cooled computing device 1200 in accordance with some embodiments. For example, one or more components of computing device 1200 may include any of the devices or structures discussed elsewhere herein. A number of components are illustrated in FIG. 12 as included in computing device 1200, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in computing device 1200 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, computing device 1200 may not include one or more of the components illustrated in FIG. 12, but computing device 1200 may include interface circuitry for coupling to the one or more components. For example, computing device 1200 may not include a display device 1203, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which display device 1203 may be coupled.

Computing device 1200 may include a processing device 1201 (e.g., one or more processing devices). As used herein, the term processing device or processor indicates a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processing device 1201 may include a memory 1221, a communication device 1222, a refrigeration/active cooling device 1223, a battery/power regulation device 1224, logic 1225, interconnects 1226, a heat regulation device 1227, and a hardware security device 1228.

Processing device 1201 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

Processing device 1201 may include a memory 1202, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, memory 1221 includes memory that shares a die with processing device 1202. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-M RAM).

Computing device 1200 may include a heat regulation/refrigeration device 1206. Heat regulation/refrigeration device 1206 may maintain processing device 1202 (and/or other components of computing device 1200) at a predetermined low temperature during operation. This predetermined low temperature may be any temperature discussed elsewhere herein.

In some embodiments, computing device 1200 may include a communication chip 1207 (e.g., one or more communication chips). For example, the communication chip 1207 may be configured for managing wireless communications for the transfer of data to and from computing device 1200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium.

Communication chip 1207 may implement any wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. Communication chip 1207 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Communication chip 1207 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 1207 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Communication chip 1207 may operate in accordance with other wireless protocols in other embodiments. Computing device 1200 may include an antenna 1213 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).