idref="DRAWINGS">FIG. 1, the terminal on the left of the NMOS transistor coupled to net N1 may be the source terminal and the terminal on the right of the NMOS transistor coupled to net N3 may be the drain terminal. However, when laying out this transistor, it may be flipped such that the drain terminal coupled to N3 is arranged on the left while the source terminal coupled to N1 is arranged on the right. In embodiments of the present disclosure, in addition to considering locations, the optimization that generates the rough placement may consider flipping one or more transistors in order to improve the overall layout.

In some embodiments, the rough placement is in a discretized coordinate system (e.g., horizontal and vertical coordinates of each transistor are specified with integer values) instead of the continuous coordinate system used for the initial placement. The discretized coordinate system may be used as input in future steps of the method 400 (including but not limited to the fabrication system), and so the procedure executed at subroutine block 406 may convert from the continuous coordinate system to the discretized coordinate system to generate the rough placement to enable the later actions of the method 400.

A non-limiting example embodiment of a suitable procedure conducted by the analytic layout engine 314 to generate the rough placement using analytic techniques is illustrated in FIG. 6. A non-limiting example embodiment of a suitable procedure conducted by the simulated annealing layout engine 316 to generate the rough placement using simulated annealing techniques is illustrated in FIG. 8. Both example procedures are discussed in further detail below.

At block 408, the layout management engine 312 partitions and optimizes the rough placement to generate a fine placement. In some embodiments, one or more traditional techniques applied for transistor-level optimization may be used to optimize the partitions, including but not limited to general combinatorial search schemes including but not limited to Satisfiability Modulo Theory (SMT), Mixed Integer Programming (MIP), graph search, branch-and-bound, and dynamic programming. Power, performance, and area optimization factors can be approximated by other objectives, including but not limited to interconnection length and diffusion sharing.

At block 410, the layout management engine 312 routes the fine placement to generate a completed design. Any suitable router may be used, including but not limited to a maze router, a line-probe router, a pattern router, a channel router, or a gridless router, and any suitable routing technique may be used, including but not limited to a rip-up and reroute technique or an iterative-improvement routing method. Techniques for routing a fine placement to generate a completed design are known to those of ordinary skill in the art, and so are not described in further detail herein for the sake of brevity.

Placement and routing are described in blocks 406-410 as separate tasks for the sake of clarity, as determining locations for the transistors and determining routes for the connections between the transistors are two goals of the method 400. However, placement and routing may be considered separate, related aspects of the single problem of integrated circuit design that may affect each other. Accordingly, in some embodiments, the placement steps may be followed by a routing step, which may then be followed by another iteration of one or more of the placement steps (such as, for example, if the initial placement is determined to not be routable at the routing step), and so on. Further, in some embodiments, the placement and routing problems may be considered concurrently by a combinatorial optimizer, with at least some blocks of the integrated circuit being placed and routed at the same time.

At block 412, the layout management engine 312 stores the completed design in a layout data store 308 of the layout computing system 310. In some embodiments, the layout management engine 312 may not store the completed design in the layout data store 308, but instead may immediately pass it to other components of the layout computing system 310. However, by storing the completed design in the layout data store 308, the layout computing system 310 may be able to update or reuse the completed design without having to repeat the optimization steps described above.

At block 414, a user interface engine 318 of the layout computing system 310 presents the completed design, receives one or more manual updates to the completed design, and stores the updated design in the layout data store 308. Often, it may be desired to make manual adjustments to the completed design. For example, a user may wish to add one or more components to the completed design, remove one or more components from the completed design, add input or output ports or vias to the completed design to allow the resultant integrated circuit to communicate with other devices, adjust a position of one or more components to better interoperate with other devices, and/or make various other types of changes. In some embodiments, the user interface engine 318 receives indicates of such changes and adjusts the completed design in response while ensuring that any design rules remain met.

In some embodiments, the user interface can include an interactive and/or searchable transistor map that can be used to identify transistors that are connected or otherwise grouped (e.g., into a Boolean logic function) that would conventionally be replaced in a mapping by a cell representation. To that end, the user interface can include a search tool configured to query the completed design and to return a subset of transistors and/or nets in accordance with the query terms. The user interface may update the presentation of the transistor map to visually emphasize the subset of transistors and/or nets that match the query terms. Additionally or alternatively, the user interface can also include data or information useful for a user of the environment, such as a value of the objective function/loss function as a function of iteration number to judge convergence, a qualitative or quantitative determination of convergence, or the like. Similarly, the layout management engine 312 can interact with the user interface to facilitate at least partial manual input with respect to one or more transistors. For example, between iterations of automated modification, a user can insert additional transistors, remove transistors, modify the net list, manually reconfigure coordinate(s) and/or orientation(s) of transistor(s), and/or add soft or hard region fences around groups of transistors.

At block 416, the layout management engine 312 provides the design from the layout data store 308 to a fabrication system to fabricate the integrated circuit. Any type of fabrication system capable of fabricating integrated circuits, including but not limited to a photolithography system, may be used.

The method 400 then proceeds to an end block and terminates.

FIG. 6 illustrates a non-limiting example embodiment of a procedure for generating a rough layout using analytic techniques according to various aspects of the present disclosure. In the procedure 600, analytic techniques take advantage of the differentiability of operations over the continuous coordinate space to optimize the locations of the transistors, and then convert the locations in the continuous coordinate space to locations in a discretize coordinate space for use by further actions of the calling method 400.

From a start block, the procedure 600 advances to block 602, where the analytic layout engine 314 conducts an optimization of the transistor locations in a continuous coordinate space using a loss function that may include a term for orientations of the transistors.

In some embodiments, the optimization minimizes a value of the loss function (also referred to as an objective function) by perturbing design points (e.g., the locations of the transistors within the continuous coordinate space) until a minimum of the value is found (or until a predetermined number of iterations have been performed). In some embodiments, perturbing design points includes flipping orientations of one or more transistors. In some embodiments, the loss function may include a term that represents orientation of one or more transistors. A subsequent design point may be found using any suitable optimization technique, including but not limited to gradient descent, genetic algorithms, and combinations thereof. The use of the continuous coordinate space at this point in the procedure 600 allows iterative techniques such as gradient descent to be effective, even though the locations in the continuous coordinate space cannot be used for fabrication.

The loss function may include one or more terms as convergence objectives. An illustrative example of a convergence objective for the optimization is the weighted sum of half-perimeter wire length (HPWL). With respect to the weighting factor, w_ijis defined as a weight for a net, for which the weighted sum of HPWL is formulated as Σw_ij*(|x_i−x_j|+|y_i−y_j|), which can be approximated using quadratic or other non-linear objectives (e.g., the distance can be constrained to rectilinear routing conventions, can use shortest linear path, can include curvilinear conventions that incorporate manufacturability limits on radius of curvature, etc.). Additional or alternative convergence objectives include but are not limited to interconnection length, transistor density, routability, timing, power, manufacturability, among others.

The objective can be used to approximate power, performance, and area optimization factors. The weighting factor w_ijmay be net specific for a given net, connecting transistor “i” and “j.” In some embodiments, a given net can connect more than two transistors. As such, weighting factor w_ijkmay be defined for a net connected to three transistors, with logical extension to nets that connect more than three transistors. In some embodiments, transistor specific weighting is applied, such that a given transistor “i” can be assigned a weight that makes it relatively more or less influential on the overall placement of the set of transistors. For example, where transistor density is used as an objective function, individual transistors can be attributed respective weights w_i.

In some embodiments, the weights w_ican be defined in terms of a density function d_ithat defines a numerical probability for a transistor to be placed in a given matrix space. The density function d_ican also be at least partially dependent on the number of transistors within a given spacing of transistor t_i(e.g., such that the probability of placing transistor t_idecreases with an increasing density of transistors in a given region of the placement matrix).

In some embodiments, one or more constraints can be applied to prevent convergence of the transistor placement matrix to a non-physical solution (e.g., two different transistors occupying the same physical space). For example, a transistor can be assigned a size in the coordinate space and/or an exclusion radius in the coordinate space (e.g., a zero-dimensional size with a (1,1) exclusion radius), where the term “exclusion radius” refers to a spacing around a given transistor “i” within which no other transistor “j” is permitted. The spacing can be defined in terms of spatial dimensions (e.g., in physical terms in a two-dimensional plane) or in the coordinate space (e.g., in index terms relative to the coordinate of the transistor). In an illustrative example, a transistor t_ican be attributed an exclusion radius of two grid spacings in x-y space, such that a second transistor t_jwill not be assigned a coordinate up to two units distant from the position of the transistor. In some embodiments, each transistor in the set of transistors can be assigned the same size, corresponding to the physical condition of transistors in fabricated integrated circuits. In some embodiments, transistors are be assigned different sizes and/or exclusion distances.

As an approach to reducing computational complexity of applying constraints, an objective function (e.g., the HPWL described above) can be modified to include a penalty term. For example, constraints on physical space (e.g., non-overlapping transistor rules) can be relaxed into the objective function using penalty terms. Similarly, a local refinement step can be included to optimize transistor placement, for example, as part of a power, performance, and/or area optimization. In an illustrative example, a subset of transistors can be translated or otherwise displaced as part of reducing the overall area of an integrated circuit including thousands of transistors.

Once the optimal locations and orientations have been determined by the optimization technique at block 602, the procedure 600 then converts the locations from the continuous coordinate space to the discrete coordinate space. Accordingly, the procedure 600 advances to block 604, where the analytic layout engine 314 sorts the transistors in the continuous coordinate space in a horizontal direction and a vertical direction. To do so, the analytic layout engine 314 may compare the locations of the transistors to each other, and may create two lists: a first list with the transistors sorted in order based on their locations on a horizontal axis, and a second list with the transistors sorted in order based on their locations on a vertical axis. If more or fewer dimensions are present in the location, additional lists may be used.

At block 606, the analytic layout engine 314 places the transistors in a plurality of rows of a discrete coordinate space according to the sort in the vertical direction and in a plurality of columns of the discrete coordinate space according to the sort in the horizontal direction to generate a preliminary discrete layout. In some embodiments, the analytic layout engine 314 may determine a number of available rows in the discrete coordinate space, and may determine a number of transistors to be placed in each row to evenly distribute the transistors throughout the rows, and a number of transistors to be placed in each column to evenly distribute the transistors throughout the columns. The analytic layout engine 314 may then process the list of transistors sorted by vertical location to place the transistors in the rows (e.g., if three transistors are to be placed in each row, the first three transistors in the list are assigned to the first row, the next three transistors in the list are assigned to the second row, and so on), and then similarly process the list of transistors sorted by horizontal location to place the transistors in the columns (e.g., if five transistors are to be placed in each column, the first five transistors in the list are placed in the first column, the next five transistors are placed in the second column, and so on). In some embodiments, certain locations may be limited to certain types of transistors (e.g., PMOS vs. NMOS), and so the placement at this point may take these constraints (and/or other fabricability constraints) into consideration.