203 may be made of hafnium oxide. The initial gate dielectric layers 203 may be used to form gate dielectric layers.

The gate electrode layers 202 may be made of metal, and the metal may include copper, aluminum, tungsten, or a combination thereof. In one embodiment, the gate electrode layers 202 may be made of tungsten.

The first spacers 204 and the second spacers 207 may be made of different materials. The second spacers 207 may be used to protect the the first conductive structures 205 from etching loss when etching the first spacers 204. In the subsequent process of etching the first spacers 204, an etching process with a larger selection ratio of the first spacers 204 to the second spacers 207 may be used to reduce etching damage on the second spacers 207.

The second spacers 207 may be made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or a combination thereof. In one embodiment, the second spacers 207 may be made of silicon nitride.

The first spacers 204 may be made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or a combination thereof. In one embodiment, the first spacers 204 may be made of silicon oxide.

The source/drain layers 206 may have doping ions, and the doping ions may be N-type or P-type. The N-type ions may include phosphorus ions, arsenic ions, or antimony ions. The P-type ions may include boron ions, boron fluoride ions or indium ions.

As shown in FIG. 3, the initial gate dielectric layers 203 and the first spacers 204 may be etched to form first grooves 208 between the first conductive structures 205 and the gate electrode layers 202 (e.g., S108 in FIG. 14). The first grooves 208 may expose sidewalls of the gate electrode layers 202, such that gate dielectric layers 209 may be formed from a portion of the initial gate dielectric layers 203 at the bottoms of the gate electrode layers 202, and gate structures may be formed with the initial gate structures.

A depth-to-width ratio of the first grooves 208 may be about 2:1 to about 10:1.

The initial gate dielectric layers 203 may be etched to remove a portion of the initial gate dielectric layers 203 on the sidewalls of the gate electrode layers 202, therefore reducing the parasitic capacitance between the gate electrode layers 202 and the first conductive structures 205.

In one embodiment, the gate dielectric layers 209 may further include a portion of the initial gate dielectric layer located on the sidewalls of the gate electrode layers 202. The first spacers 204 may be etched to form protective layers 210. The protective layers 210 may allow a small amount of the initial gate dielectric layers 203 on the sidewalls of the gate electrode layers 202 to remain, to reduce the occurrence of damage to the gate dielectric layers 209 caused by over-etching and improve the performance of the gate dielectric layers 209.

In one embodiment, the initial gate dielectric layers 203 and the first spacers 204 may be removed by etching in a same process. Specifically, in one embodiment, the material of the initial gate dielectric layer 203 may be hafnium oxide, and the material of the first spacers 204 may be silicon oxide, which may be etched with a hydrofluoric acid solution to form the first grooves 208.

In another embodiment, the first spacers 204 may be etched first, and then the initial gate dielectric layers 203 may be etched.

As shown in FIG. 4, a second dielectric layer 211 may be formed on the surface of the first dielectric layer and the gate structures (e.g., S110 in FIG. 14). The second dielectric layer 211 may close tops of the first grooves 208, to form air spacers 212 between the first conductive structures 205 and the gate electrode layers 202.

In one embodiment, the second dielectric layer 211 may be also located on top surfaces of the second spacers 207 and the first conductive structures 205.

The second dielectric layer 211 may be formed by a plasma-enhanced chemical vapor deposition process.

In one embodiment, process parameters for forming the second dielectric layer 211 may include: a reaction gas of a mixed gas of silane, nitrogen, oxygen and nitrous oxide; a gas flow rate of about 10 standard milliliters per minute to about 30,000 standard milliliters per minute; a pressure of about 0.5 torr to about 20 torr; power of about 100 watts to about 2000 watts. The reaction gas of the deposition process may be preferentially deposited on the tops of the first grooves 208, such that the first grooves 208 may be sealed to form sealed cavities 212.

The second dielectric layer 211 may be made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

The air spacers 212 may be formed between the first conductive structures 205 and the gate electrode layers 202, and the air spacers 212 may have a relatively small dielectric constant for isolating the gate electrode layers 202 and the first conductive structures 205. Correspondingly, the parasitic capacitance between the gate electrode layers 202 and the first conductive structures 205 may be reduced, therefore improving the performance of the device.

FIGS. 5-8 illustrate semiconductor structures corresponding to certain stages of forming another exemplary semiconductor structure according to various disclosed embodiments of the present disclosure.

As shown in FIG. 5 which is based on FIG. 2, before forming the first grooves, a third dielectric layer 301 may be formed on a surface of the first dielectric layer, the initial gate structures, and the first conductive structures 205. Second grooves 302 may be formed in the third dielectric layer 301, to expose the top surfaces of the initial gate dielectric layers 203 and the first spacers 204.

In one embodiment, the third dielectric layer 301 may be also located on the top surfaces of the first spacers 204 and the second spacers 207.

The third dielectric layer 211 may be made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

The second grooves 302 may be used to expose the top surfaces of the initial gate dielectric layers 203 and the first spacers 204, to facilitate subsequent etching of the initial gate dielectric layers 203 and the first spacers 204. Also, the third dielectric layer 301 may protect the gate structures and the surface of the first conductive structures 205 during the etching process.

Subsequently, the initial gate dielectric layers 203 and the first spacers 204 may be etched to form the first grooves between the first conductive structures 205 and the gate electrode layers 202. The first grooves 208 may expose the sidewalls of the gate electrode layers 202, such that gate dielectric layers 209 may be formed from a portion of the initial gate dielectric layers 203 at the bottoms of the gate electrode layers 202.

In one embodiment, the first grooves may be formed by a two-step etching process. That is, the first spacers 204 may be etched before etching the initial gate dielectric layers 203. In other embodiments, the initial gate dielectric layers and the first spacers may be removed by etching in a same process.

Formation of the first grooves is shown in FIG. 6 and FIG. 7.

As shown in FIG. 6, the first spacers 204 may be etched to a target depth, and a remaining portion of the first spacers 204 may form protective layers 303.

In one embodiment, the first spacers 204 may be made of silicon nitride and the second sidewall spacers 207 may be made of silicon nitride carbide. To avoid the influence of the etching process of the first spacers 204 on the second spacers 207, a process with a larger selection ratio for the first spacers 204 and the second spacers 207 may be selected. In one embodiment, the first spacers 204 may be etched with a phosphoric acid solution.

The protective layers 303 may be used to protect the subsequently formed gate dielectric layers from damage during the etching process, which may be beneficial to improve the gate leakage current of the formed device and the performance of the device.

As shown in FIG. 7, after forming the protective layers 303, the initial gate dielectric layers 203 may be etched.

In one embodiment, the initial gate dielectric layer 203 may be made of hafnium oxide, and may be etched with a hydrofluoric acid solution.

The initial gate dielectric layers 203 and the first spacers 204 may be etched to form first grooves 304 between the first conductive structures 205 and the gate electrode layers 202. The first groove 304 may expose the sidewalls of the gate electrode layers 202. A portion of the initial gate dielectric layers 203 at the bottoms of the gate electrode layers 202 may be used to form the gate dielectric layers, and gate structures may be formed from the initial gate structures.

The first grooves 304 may be subsequently used to form air spacers.

The initial gate dielectric layers 203 may be etched to remove the initial gate dielectric layers 203 on the sidewalls of the gate electrode layers 202, therefore reducing the parasitic capacitance between the gate electrode layers 202 and the first conductive structures 205.

As shown in FIG. 8, a second dielectric layer 305 may be formed on the surface of the first dielectric layer and the gate structures. The second dielectric layer 305 may seal the tops of the first grooves 304, to form air spacers 306 between the first conductive structures 205 and the gate electrode layers 202.

In one embodiment, the second dielectric layer 305 may be also located in the second grooves 302.

The second dielectric layer 305 may be made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

The air spacers 306 may be formed between the first conductive structures 205 and the gate electrode layers 202, and the air spacers 306 may have a relatively small dielectric constant for isolating the gate electrode layers 202 and the first conductive structures 205. Correspondingly, the parasitic capacitance between the gate electrode layers 202 and the first conductive structures 205 may be reduced, therefore improving the performance of the device.

FIGS. 9-13 illustrate semiconductor structures corresponding to certain stages of forming another exemplary semiconductor structure according to various disclosed embodiments of the present disclosure.

As shown in FIG. 9 which is based on FIG. 2, before forming the first grooves, a third dielectric layer 401 may be formed on the surface of the first dielectric layer, the initial gate structures, and the first conductive structures 205.

In one embodiment, the third dielectric layer 401 may be also located on the top surfaces of the first spacers 204 and the second spacers 207.

The third dielectric layer 401 may be made of a material including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

As shown in FIG. 10, second conductive structures 402 may be formed in the third dielectric layer 401. The second conductive structures 402 may be located on the surfaces of the first conductive structures 205. Third conductive structure 403 may be formed in the third dielectric layer 401. The third conductive structure 403 may be located on the surfaces of the gate electrode layers 202.

As shown in FIG. 11, the third dielectric layer 401 may be removed to form second grooves 404. The second grooves 404 may expose top surfaces of the initial gate dielectric layers 203 and the first spacers 204.

The second grooves 404 may expose the top surfaces of the initial gate dielectric layers 203 and the first spacers 204, to prepare for subsequent etching of the initial gate dielectric layers 203 and the first spacers 204.

As shown in FIG. 12, the initial gate dielectric layers 203 and the first spacers 204 may be etched to form first grooves 405 between the first conductive structures 205 and the gate electrode layers 202, and form protective layers 406 after the etching of the first spacers 204. The first groove 405 may expose the sidewalls of the gate electrode layers 202. Gate dielectric layers 407 may be formed from a portion of the initial gate dielectric layers 203 at the bottoms of the gate electrode layers 202, and gate structures may be formed from the initial gate structures.

A depth-to-width ratio of the first grooves 208 may be about 2:1 to about 10:1.

In one embodiment, the initial gate dielectric layers 203 and the first spacers 204 may be removed by etching in a same process. Specifically, in one embodiment, the material of the initial gate dielectric layer