FIGS. 3A and 3B are graphs showing simulation results of characteristics of the semiconductor device according to the first embodiment.

In FIGS. 3A and 3B, the horizontal axis is the time (a. u.). In FIG. 3A, the vertical axis is a collector-emitter current Ic (a. u.) and the collector-emitter voltage Vce (a. u.). In FIG. 3B, the vertical axis is the loss (a. u.). “a. u.” means arbitrary units.

FIGS. 3A and 3B show simulation results of the characteristics of an experimental example 1 having a structure in which the gate part 41 including the three gate electrodes 42 and the dummy part 43 including the three dummy electrodes 44 were alternately arranged and the gate potential was applied to the dummy electrode 44 located at the position next to the gate part 41, and an experimental example 2 in which the emitter potential was applied to the dummy electrode 44 located at the position next to the gate part 41.

A gate potential was applied to the gate electrode 42 in the experimental examples 1 and 2. In the experimental examples 1 and 2, the gate potential was set to 15 V, and the emitter potential was set to 0 V.

In FIG. 3A, the change over time of the collector-emitter current Ic and the collector-emitter voltage Vce at turn-on of the experimental example 1 are shown by broken lines, and the change over time of the collector-emitter current Ic and the collector-emitter voltage Vce at turn-on of the experimental example 2 are shown by solid lines.

In FIG. 3B, the change over time of the loss at turn-on of the experimental example 1 is shown by a broken line, and the change over time of the loss at turn-on of the experimental example 2 is shown by a solid line.

In the experimental example 1 as illustrated in FIGS. 3A and 3B, compared to the experimental example 2, the fall characteristic of the collector-emitter voltage Vce at turn-on was good, and the loss at turn-on was reduced.

Therefore, this suggests that according to the first embodiment, compared to when the first potential (e.g., the emitter potential) is applied to the dummy electrode 44 located at the position next to the gate part 41, the loss at turn-on can be reduced by applying the third potential (e.g., the gate potential) that is greater than the first potential to the dummy electrode 44 located at the position next to the gate part 41.

FIG. 4 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment.

In the semiconductor device 100A according to the first modification of the first embodiment as illustrated in FIG. 4, among the dummy electrodes 44, a resistance part 60 is provided between the gate potential G and the dummy electrode 44 located at the position next to the gate part 41. Otherwise, the semiconductor device 100A is substantially the same as the semiconductor device 100 described above.

More specifically, the resistance part 60 is provided between the gate potential G and the dummy electrodes 44a, 44c, 44d, and 44f. Thereby, the third potential that is applied to the dummy electrodes 44a, 44c, 44d, and 44f is less than the second potential (the gate potential G). Thus, the third potential may be adjusted by providing the resistance part 60, etc.

In the semiconductor device 100A according to the first modification of the first embodiment as well, by applying the third potential that is greater than the first potential to the dummy electrode 44 located at the position next to the gate part 41, the hole accumulation rate can be ensured, and the fall characteristic of the collector-emitter voltage Vce at turn-on can be improved. The loss at turn-on can be reduced thereby.

FIG. 5 is a plan view showing a semiconductor device according to a second modification of the first embodiment.

FIG. 6 is a cross-sectional view showing the semiconductor device according to the second modification of the first embodiment.

FIG. 6 is a cross-sectional view along line B1-B2 shown in FIG. 5.

In the semiconductor device 100B according to the second modification of the first embodiment as illustrated in FIGS. 5 and 6, the second electrode 30 includes a first conductive part 31 and a second conductive part 32. The first conductive part 31 is not illustrated in FIG. 5.

The first conductive part 31 is located on the semiconductor part 20. The second conductive part 32 is located under the first conductive part 31, The second conductive part 32 is located in the semiconductor part 20. At least a portion of the second conductive part 32 is positioned between two gate electrodes 42 next to each other in the X-direction. In the example, the second conductive part 32 is located between the two gate electrodes 42 next to each other, between the two dummy electrodes 44 next to each other, and between the gate electrode 42 and the dummy electrode 44 next to each other.

In the example, the third semiconductor region 23 includes a first part 23a and a second part 23b. The second part 23b is located on the first part 23a, The fourth semiconductor region 24 is located on the first part 23a. In the example, the fourth semiconductor region 24 and the second part 23b of the third semiconductor region 23 are alternately arranged in the X-direction along line B1-B2. In the example, the fourth semiconductor region 24 and the second part 23b of the third semiconductor region 23 are alternately arranged in the Y-direction at the side surface of the gate electrode 42, In the example, the dummy part 43 is located in the second part 23b of the third semiconductor region 23.

In the example, the fifth semiconductor region 25 is located under the second conductive part 32. The fifth semiconductor region 25 is located between the second conductive part 32 and the first part 23a of the third semiconductor region 23 in the Z-direction. The fifth semiconductor region 25 is arranged with the first part 23a of the third semiconductor region 23 in the X-direction. Otherwise, the example is substantially the same as the semiconductor device 100 described above.

The second conductive part 32 that is located between two mutually-adjacent gate electrodes 42 is located in the fourth semiconductor region 24. The second conductive part 32 that is located between the two mutually-adjacent gate electrodes 42 extends in the Z-direction from the lower end of the first conductive part 31 through the fourth semiconductor region 24 to the first part 23a of the third semiconductor region 23. In other words, the second conductive part 32 that is located between the two mutually-adjacent gate electrodes 42 is arranged with the fourth semiconductor region 24 and the first part 23a of the third semiconductor region 23 in the X-direction.

The second conductive part 32 that is located between the two mutually-adjacent dummy electrodes 44 is located in the second part 23b of the third semiconductor region 23. The second conductive part 32 that is located between the two mutually-adjacent dummy electrodes 44 extends in the Z-direction from the lower end of the first conductive part 31 through the second part 23b of the third semiconductor region 23 to the first part 23a of the third semiconductor region 23. In other words, the second conductive part 32 that is located between the two mutually-adjacent dummy electrodes 44 is arranged with the first and second parts 23a and 23b of the third semiconductor region 23 in the X-direction.

The second conductive part 32 that is located between the gate electrode 42 and the dummy electrode 44 that are next to each other is located at the boundary between the fourth semiconductor region 24 and the second part 23b of the third semiconductor region 23, The second conductive part 32 that is located between the gate electrode 42 and the dummy electrode 44 that are next to each other extends in the Z-direction from the lower end of the first conductive part 31 through the second part 23b of the third semiconductor region 23 and the fourth semiconductor region 24 to the first part 23a of the third semiconductor region 23. In other words, the second conductive part 32 that is located between the gate electrode 42 and the dummy electrode 44 that are next to each other is arranged with the fourth semiconductor region 24 and the first and second parts 23a and 23b of the third semiconductor region 23 in the X-direction.

In the semiconductor device 100B according to the second modification of the first embodiment as well, by applying the third potential that is greater than the first potential to the dummy electrode 44 located at the position next to the gate part 41, the hole accumulation rate can be ensured, and the fall characteristic of the collector-emitter voltage Vce at turn-on can be improved. The loss at turn-on can be reduced thereby.

FIG. 7 is a plan view showing a semiconductor device according to a second embodiment.

FIG. 8 is a cross-sectional view showing the semiconductor device according to the second embodiment.

FIG. 8 is a cross-sectional view along line C1-C2 shown in FIG. 7.

In the semiconductor device 200 according to the second embodiment as illustrated in FIGS. 7 and 8, the gate part 41 includes at least two gate electrodes 42. In the semiconductor device 200, the dummy part 43 includes at least one dummy electrode 44. Otherwise, the semiconductor device 200 is substantially the same as the semiconductor device 1003 described above. The first conductive part 31 is not illustrated in FIG. 7.

More specifically, the gate part 41 includes at least a first gate electrode 42x and a second gate electrode 42y. The first gate electrode 42x is located at one end of the fourth semiconductor region 24 in the X-direction. The second gate electrode 42y is located at the other end of the fourth semiconductor region 24 in the X-direction. The first gate electrode 42x is positioned between the fourth semiconductor region 24 and the second part 23b of the third semiconductor region 23 in the X-direction. The second gate electrode 42y is positioned between the fourth semiconductor region 24 and the second part 23b of the third semiconductor region 23 in the X-direction. The fourth semiconductor region 24 is located between the first gate electrode 42x and the second gate electrode 42y in the X-direction.

In the X-direction, the second part 23b of the third semiconductor region 23 is located between one gate part 41 (e.g., the gate part 41a) and another gate part 41 (e.g., the gate part 41b or the gate part 41c) next to the one gate part 41. One X-direction side surface of the first gate electrode 42x faces the second part 23b of the third semiconductor region 23. The other X-direction side surface of the first gate electrode 42x faces the fourth semiconductor region 24. One X-direction side surface of the second gate electrode 42y faces the fourth semiconductor region 24. The other X-direction side surface of the second gate electrode 42y faces the second part 23b of the third semiconductor region 23.

The gate part 41 may further include a third gate electrode 42z located between the first gate electrode 42x and the second gate electrode 42y. The third gate electrode 42z is located in the fourth semiconductor region 24. In the example, the gate part 41 includes one third gate electrode 42z. That is, in the example, the gate part 41 is made of three gate electrodes 42. The number of the third gate electrodes 42z included in the gate part 41 may be zero, one, two, or more.

In the example, the dummy part 43 includes one dummy electrode 44. In the example, the dummy part 43 is made of one dummy electrode 44, That is, in the example, the number of the dummy electrodes 44 included in the dummy part 43 is one. The number of the dummy electrodes 44 included in the dummy part 43 may be one, two, or more.

In the example, the structure body 40 includes the gate parts 41a, 41b, and 41c and the dummy parts 43a and 43b. These parts are arranged in the order of the gate part 41b, the dummy part 43a, the gate part 41a, the dummy part 43b, and the gate part 41c in the X-direction.

The gate parts 41a, 41b, and 41c each include the first gate electrode 42x, the second gate electrode 42y, and the third gate electrode 42z. The dummy part 43a includes the dummy electrode 44a. The dummy part 43b includes the dummy electrode 44b.

In the example, the first potential is applied to the second electrode 30 and the dummy electrode 44. The first potential is, for example, the emitter potential E. The first potential is, for example, 0 V, On the other hand, the second potential is applied to the gate electrode 42. The second potential is, for example, the gate potential G. The second potential is greater than the first potential. The second potential is, for example, 15 V.

Operations and effects of the semiconductor device 200 will now be described.

The semiconductor device is set to the on-state when a voltage that is not less than a threshold is applied to the gate electrode 42 in a state in which a positive voltage with respect to the second electrode 30 (the emitter electrode) is applied to the first electrode 10 (the collector electrode). At this time, a channel (an inversion layer) is formed in the region of the third semiconductor region 23 at the first insulating part 51 (gate insulating film) vicinity. Electrons are injected from the fourth semiconductor region 24 via the channel into the second semiconductor region 22; and holes are injected from the first semiconductor region 21 into the second semiconductor region 22. Subsequently, when the voltage applied to the gate electrode 42 drops below the threshold, the channel in the third semiconductor region 23 disappears, and the semiconductor device is set to the off-state.

The capacitance of the gate electrode 42 can be reduced by providing the structure body 40, in which the gate part 41 including the gate electrode 42 and the dummy part 43 including the dummy electrode 44 are alternately arranged inside the semiconductor part 20, and by the gate part 41 including the first gate electrode 42x located at one end of the fourth semiconductor region 24 and the second gate electrode 42y located at the other end of the fourth semiconductor region 24. The response speed can be increased thereby. Also, the hole accumulation rate can be ensured, and the fall characteristic of the collector-emitter voltage Vce at turn-on can be improved. The loss at turn-on can be reduced thereby. The simulation results of the characteristics of the semiconductor device according to the second embodiment are similar to the simulation results of the characteristics of the semiconductor device according to the first embodiment illustrated in FIGS. 3A and 3B above.

If the number of the dummy electrodes 44 included in the dummy part 43 is one, compared to, for example, the second modification of the first embodiment, the gate capacitance can be reduced, and the drive loss can be reduced. When the gate potential G is applied to all of the dummy electrodes 44 without providing the dummy electrode 44 to which the emitter potential E is applied, a negative capacitance (a phenomenon of the gate charge decreasing when the gate potential G is increased) occurs when a load short circuit occurs, etc., and gate oscillation easily occurs. In contrast, the gate oscillation can be suppressed by providing the dummy electrode 44 to which the emitter potential E is applied. In the example, the surface area ratio of the fourth semiconductor region 24 supplying the electron current when switched on is equal to that of the second modification of the first embodiment shown in FIGS. 5 and 6. However, because the number of electrodes to which the gate potential G is applied is low, the gate capacitance is small, and the drive loss is small. Also, the gate driver that drives the IGBT can be made smaller. The example of FIG. 8 has the advantage that the negative capacitance occurs less easily because the number of successive adjacent electrodes to which the adjacent gate potential G is applied is three, which is less than the five of the example of FIG. 6. However, other than the load of the gate driver, it is not always better for the gate capacitance to be small depending on the application; it is therefore favorable to selectively use the structure of the second embodiment and structures such as that of the first embodiment.

Embodiments may include the following configurations.

Configuration 1

A semiconductor device, comprising:

- a first electrode;
- a semiconductor part including
  - a first semiconductor region located on the first electrode, the first semiconductor region being of a p-type,
  - a second semiconductor region located on the first semiconductor region, the second semiconductor region being of an n-type,
  - a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the p-type,
  - a fourth semiconductor region located on the third semiconductor region, the fourth semiconductor region being of the n-type, and
  - a fifth semiconductor region located on the third semiconductor region, the fifth semiconductor region being of the p-type;
- a second electrode located on the semiconductor part;
- a structure body including a gate part and a dummy part alternately arranged in a second direction perpendicular to a first direction, the gate part including at least one gate electrode, the dummy part including at least two dummy electrodes, the first direction being from the first semiconductor region toward the second semiconductor region; and
- an insulating part located between the gate electrode and the semiconductor part,
- the gate part being located in the fourth semiconductor region,
- a first potential being applied to the second electrode,
- a second potential being applied to the gate electrode,
- the second potential being greater than the first potential,
- a third potential being applied to the dummy electrode located at a position next to the gate part,
- the third potential being greater than the first potential.
  
  Configuration 2

The device according to configuration 1, wherein

- the fourth semiconductor region and the fifth semiconductor region are alternately arranged in the second direction, and
- the dummy parts are located in the fifth semiconductor region.
  
  Configuration 3

The device according to configuration 1, wherein

- the second electrode includes: