In some embodiments, the mesa structure extends from the first semiconducting layer such that the growth surface comprises a portion of a surface of the first semiconducting layer.

In some embodiments, the fourth semiconducting layer comprises GaN.

In some embodiments, the fourth semiconducting layer is provided on the growth surface to provide an inclined sidewall portion extending from a mesa portion of the fourth semiconducting layer on the mesa surface of the third semiconducting layer towards the second semiconducting layer.

In some embodiments, the monolithic growth stack further comprises a masking layer provided on the growth surface of the monolithic growth stack, the masking layer comprising an aperture aligned with the mesa surface of the monolithic growth stack.

In some embodiments, the monolithic LED stack is selectively provided only on the mesa surface of the monolithic growth stack.

The LED precursor, and the methods of forming the LED precursor according to the first and second aspects of the disclosure may, in some embodiments provide a LED array precursor comprising a plurality of LED precursors and a method of forming thereof. The plurality of LED precursors may be arranged in a two-dimensional array in which each of the LED precursors are spaced apart from the other LED precursors.

The LED precursor, LED array precursor, and the methods of forming the LED precursor and LED array precursor according to the first and second aspects of the disclosure may, in some embodiments provide micro LED precursors and micro LED array precursors. A micro LED array precursor is an array of micro LED precursors. A micro LED precursor may comprise a monolithic LED stack which has a surface area dimension in a plane aligned with the first semiconducting layer of less than 100 μm×100 μm. For example, in some embodiments, the micro LED precursors may have a surface area of less than 10⁻⁸m².

BRIEF DESCRIPTION OF THE FIGURES

The disclosure will now be described in relation to the following non-limiting figures. Further advantages of the disclosure are apparent by reference to the detailed description when considered in conjunction with the figures in which:

FIG. 1 shows a diagram of an intermediate stage of forming the monolithic growth stack according to a first embodiment of the disclosure;

FIG. 2 shows a diagram of an intermediate stage of forming the monolithic growth stack according to the first embodiment of the disclosure;

FIG. 3 shows a diagram of an intermediate stage of forming a monolithic growth stack according to the first embodiment of the disclosure;

FIG. 4 shows a diagram of a plurality of monolithic growth stacks according to embodiments of the disclosure;

FIG. 5 shows a diagram of a plurality of LED precursors according to a first embodiment of the disclosure;

FIG. 6 shows a diagram of a plurality of monolithic growth stacks according to a second embodiment of the disclosure;

FIG. 7 shows a diagram of a plurality of LED precursors according to a second embodiment of the disclosure;

FIG. 8 shows a diagram of a plurality of monolithic growth stacks according to a third embodiment of the disclosure;

FIG. 9 shows a diagram of a plurality of LED precursors according to a third embodiment of the disclosure.

DETAILED DESCRIPTION

According to a first embodiment, a method for forming a LED precursor 1 is provided.

By the term “precursor” in LED precursor, it is noted that the LED precursor described does not necessarily include the electrical contacts for the LED such as to allow the emission of light, nor the associated circuitry. Of course, the method of forming the LED precursor of the first embodiment does not preclude the addition of further electrical contacts and associated circuitry. As such use of the term precursor in this disclosure is intended to include the finalised product (i.e. a LED, a LED array etc.).

FIGS. 1 to 5 show diagrams of the LED precursor as it is formed according to the method of the first embodiment. The method according to the first embodiment comprises forming a monolithic growth stack 10 and a monolithic LED stack 20. The monolithic LED stack 20 is formed on a growth surface 11 of the monolithic growth stack 10. According to the method of the first embodiment, the monolithic growth stack 10 comprises a first semiconducting layer 12, a second semiconducting layer 14, and a third semiconducting layer 16.

A monolithic growth stack refers to the provision of a stack of layers forming a growth surface for an LED which are formed as a single piece. That is to say, the monolithic growth stack 10 is formed as a single piece.

A monolithic LED stack refers to the provision of a stack of layers forming an LED which are formed as a single piece. That is to say, the monolithic LED stack is formed as a single piece on the growth surface 11 of the monolithic growth stack 10.

In the method of the first embodiment, a plurality of LED precursors 1 are formed in a single formation process. The plurality of LED precursors 1 are formed as an array of LED precursors. As such, the method according to the first embodiment provides a method of forming a LED array precursor comprising a plurality of LED precursors.

As shown in FIG. 1, forming the monolithic growth stack 10 comprises forming a first semiconducting layer 12. In the embodiment of FIG. 1 the first semiconducting layer 12 comprises a Group III-nitride. For example, the first semiconducting layer may comprise GaN. In some embodiments, the first semiconducting layer may be an undoped semiconducting layer (i.e. not intentionally doped). In other embodiments, the first semiconducting layer 12 may be a doped semiconducting layer (e.g. comprising an n-type dopant such as Si).

The first semiconducting layer 12 may be formed on a substrate (not shown in FIG. 1). The substrate may provide a growth surface for the first semiconducting layer 12. The substrate may be a substantially planar substrate. The substrate may have an in-plane lattice constant which is configured to correspond to the in-plane lattice constant of the first semiconducting layer 12 to reduce lattice mismatch. Various substrates suitable for the growth of a first semiconducting layer 12 comprising a Group III-nitride are known to the skilled person. For example, the substrate may be a sapphire substrate, or a silicon substrate. The substrate may comprise one or more buffer layers configured to provide a substrate surface suitable for the formation of Group III-nitride layers. The substrate may be provided such that the first semiconducting layer 12 is grown on the substrate such that a (0001) crystal plane of the first semiconducting layer 12 is aligned with the substrate surface. As such, the first semiconducting layer 12 may have a (0001) crystal plane orientation.

The first semiconducting layer may be formed using any suitable process for the fabrication of Group III nitride semiconducting layers. For example, the first semiconducting layer 12 may be formed using a Metal Organic Chemical Vapour Deposition process (MOCVD), or a Molecular Beam Epitaxy (MBE) process.

As shown in FIG. 1, a second semiconducting layer 14 is formed on the first semiconducting layer 12. The second semiconducting layer 14 is formed on a first surface 13 of the first semiconducting layer 12. The first semiconducting surface 13 is the surface of the first semiconducting layer 12 which is provided on an opposite side of the first semiconducting layer 12 to the substrate. As such, the first semiconducting layer 12 is provided between the second semiconducting layer 14 and the substrate.

The second semiconducting layer 14 comprises a Group III-nitride. The second semiconducting layer 14 has a first composition including a donor dopant, such that the second semiconducting layer has a donor density of at least 5×10¹⁸cm⁻³. In some embodiments, the donor density of the second semiconducting layer may be at least: 1×10¹⁹cm⁻³, 3×10¹⁹cm⁻³, 5×10¹⁹cm⁻³, 7×10¹⁹cm⁻³, or 1×10²⁰cm⁻³. As such, the second semiconducting layer 14 is an n-type semiconducting layer. In particular, the second semiconducting layer 14 has a higher donor dopant density than the first semiconducting layer 12. The second semiconducting layer 14 may comprise any suitable donor dopant. For example, the second semiconducting layer 14 may comprise a donor dopant including at least one of: Si, and Ge. The second semiconducting layer 14 is provided with a relatively high donor density in order to allow for targeted formation of pores in the porosity treatment step described below. By providing the second semiconducting layer 14 with a relatively high donor dopant density the porosity treatment selectively targets the second semiconducting layer 14.

The second semiconducting layer 14 may be formed at a substantially continuous layer across the major surface of the first semiconducting layer 12. As such, the first and second semiconducting layers 12, 14 may be provided substantially continuously across a substrate. The second semiconducting layer 14 has a second surface 15 on an opposite side of the second semiconducting layer 14 to the first semiconducting layer 12.

The second surface 15 of the second semiconducting layer 14 has a first in-plane lattice constant. The second semiconducting layer 14 may have a wurtzite crystal structure. In some embodiments, the second semiconducting layer 14 may be formed on the first semiconducting layer 12 having a (0001) crystal plane provided parallel to the first surface 13. So, for second semiconducting layer 14 having a second surface aligned with a (0001) crystal plane, an in-plane lattice constant may be a constant reflecting the a (or b) lattice constants.

In some embodiments, the second semiconducting layer 14 may have a thickness in the direction normal to the substrate or at least 50 nm. In some embodiments, the second semiconducting layer 14 may have a thickness of no greater than 2000 nm.

In some embodiments the first semiconducting layer 12 may have a thickness of at least 100 nm. In some embodiments, the first semiconducting layer 12 may have thickness no greater than 2000 nm.

The second semiconducting layer 14 may be formed using any suitable process for the fabrication of Group III nitride semiconducting layers. For example, a MOCVD process or a MBE processes. As such, the second semiconducting layer 14 may be formed in a similar manner and using similar equipment to the first semiconducting layer 12.

As shown in FIG. 2, following the formation of the second semiconducting layer 14, the third semiconducting layer 16 is formed on a major surface of the second semiconducting layer 14. As such, the third semiconducting layer 16 is formed on an opposite side of the second semiconducting layer 14 to the first semiconducting layer 12. The third semiconducting layer 16 provides a growth surface 11 of the monolithic growth stack 10.

The third semiconducting layer 16 comprises a Group III-nitride. The third semiconducting layer 16 has a second composition which is different to the first composition of the second semiconducting layer 14. The difference in composition between the second semiconducting layer 14 and the third semiconducting layer 16 results in the formation of the third semiconducting layer 16 under compressive strain. That is to say, the difference in in-plane lattice constants of the second and third semiconducting layers results in the as-formed third semiconducting layer 16 being under compressive stain. As such, an in-plane lattice constant of an unstrained thin film having the second composition (of the third semiconducting layer 16) would be greater than an in-plane lattice constant of an unstrained thin film having the first composition (of the second semiconducting layer 14).

The third semiconducting layer 16 is formed with a crystal structure which may be coherent with the second semiconducting layer 14. As such, the interface between the third semiconducting layer 16 and the second semiconducting layer 14 may be a coherent interface. Following a heat treatment process (discussed in more detail below), the third semiconducting layer 16 relaxes to form a strain relaxed third semiconducting layer 16. The strain relaxed third semiconducting layer 16 has strain relaxed surface forming part of the growth surface 11 of the monolithic growth stack 10 with a second in-plane lattice constant. The second in-plane lattice constant is larger than the first in-plane lattice constant of the second semiconducting layer 14. In some embodiments, the strain relaxed third semiconducting layer 16 may have a wurtzite crystal structure, similar to the first and second semiconducting layers 12, 14. In some embodiments, the third semiconducting layer 16 may be formed on the first and second semiconducting layers 12, 14 with a (0001) crystal plane provided parallel to the first and second surfaces 13, 15.

For example, in the embodiment of FIG. 2, the third semiconducting layer 16 may comprise In_XGa_1-XN, where 0<X≤1. In particular, in some embodiments the third semiconducting layer 16 may comprise In_XGa_1-XN, where 0.03<X≤0.2. Accordingly, the In content of the third semiconducting layer 16 may be selected to provide an mesa surface with a desired in-plane lattice constant.

In the embodiment of FIG. 2, the first composition of the second semiconducting layer 14 comprises GaN. The second composition of the third semiconducting layer 16 may comprise In_XGa_1-XN, where 0<X≤1. Accordingly, the formation of the third semiconducting layer 16 having the second composition and the second semiconducting layer 14 having the first composition will result in the third semiconducting layer 16 being formed on the second semiconducting layer 12 under compressive strain.

In some embodiments, the third semiconducting layer 16 may be a substantially undoped layer. That is to say, the third semiconducting layer 16 may be formed without any intentional doping. For example, in the method of forming the first embodiments, the third semiconducting layer 16 is a substantially undoped layer. In some embodiments, the third semiconducting layer 16 may comprise a dopant, for example a donor dopant. In embodiments where the third semiconducting layer includes a dopant, the third semiconducting layer may be doped with a donor density no greater than the donor density of the second semiconducting layer 14. For example, in some embodiments, the donor density of the third semiconducting layer 15 may be no greater than: 50%, 25%, 10%, 5%, 1% or 0.1% of the donor density of the second semiconducting layer 14.

In some embodiments, the third semiconducting layer 16 may have a thickness of at least 200 nm. In some embodiments, the third semiconducting layer 16 may have thickness no greater than 10 μm. For example, the third semiconducting layer 16 in FIG. 2 may have a thickness of at least 1 μm and a thickness of no greater than 10 μm.

As shown in FIG. 2, the third semiconducting layer 16 is a bulk semiconducting layer formed from a substantially continuous layer of a Group III-nitride semiconductor. It will be appreciated that the third semiconducting layer 16 is provided in order to form a strain relaxed surface (growth surface 11) for the formation of the monolithic LED stack 20. In other embodiments, the third semiconducting layer 16 may comprise a plurality of Group III-nitride layers forming a superlattice structure. For example, the third semiconducting layer 16 may comprise a plurality of first and second Group III-nitride layers arranged in an alternating stack, wherein the first and second Group III-nitride layers have different lattice constants. For example, one example of a superlattice structure is an alternating stack of layers of In_YGa_1-YN, where 0<Y≤1, and layers of GaN.

Following the formation of the third semiconducting layer 16, the second semiconducting layer 14 is subjected to a porosity treatment process in order to increase an areal porosity of the second semiconducting layer 14 to at least 15%. Methods for increasing the porosity of a Group III nitride layer are known to the skilled person. For example, “In-plane bandgap control in porous GaN through electroless wet chemical etching”, Xiuling Li, Young Woon-Kim et al., Applied Physics Letters, Vol. 8, no. 6, 11 Feb. 2002, describes several processes for increasing the porosity of an n-type doped Group III-nitride layer.

In the methods according to this disclosure, the second semiconducting layer 14, which has a donor density of at least 5×10¹⁸cm⁻³, may be selectively subjected to the porosity treatment to increase an areal porosity of the second semiconducting layer. The donor density of the second semiconducting layer allows the porosity treatment process to selectively increase the porosity of the second semiconducting layer 14.

For example, the porosity treatment may comprise subjecting the layers of the monolithic growth stack to an electrochemical treatment process. The electrochemical treatment process may comprise submerging the monolithic growth stack in a bath of oxalic acid. Electrical connections are made between the bath of oxalic acid and the monolithic growth stack 10. An electric current is passed between the electrical contacts of the oxalic acid bath and the monolithic growth stack in order to electrochemically form pores within the second semiconducting layer 14. In some embodiments, the oxalic acid baths comprises an oxalic acid solution having a concentration of between 0.03M and 0.3M. In other embodiments the oxalic acid bath may be substituted for other electrolytes such as KOH or HCl. The level of electrical bias applied to the electrochemical process will depend on the electrochemical solution used and the relative dimensions of the bath and the monolithic growth stack 10. Further examples of porosity treatments are described in ACS Applied Nano Materials, 2020, 3, 399-402 and US 2017/0237234.

The porosity treatment process results in the formation, or an increase in the size of, pores present in the second semiconducting layer 14. The porosity of the second semiconducting layer 14 may be characterised by an areal porosity. Areal porosity is the area fraction of pores present in a cross-section through the material (i.e. through the second semiconducting layer 14). In some embodiments, the porous semiconducting layer 14′ has an areal porosity of at least 15%. In some embodiments, the porous semiconducting layer 14′ has an areal porosity of at least 30%. By providing the porous semiconducting layer 14′ with such an areal porosity, the third semiconducting may strain-relax to a greater degree during a subsequent heat treatment process. Importantly, the provision of the porous semiconducting layer 14′ allows for the propagation of misfit dislocations in the porous semiconducting layer 14′ as half loop dislocations. As such, the strain relaxation of the third semiconducting layer 16 results in the preferential propagation of half loop dislocations in the porous semiconducting layer 14′ rather than the propagation of threading dislocations in the third semiconducting layer 16. Thus, the defect density in the third semiconducting layer 16 may be reduced by the provision of the porous semiconducting layer 14′.

In some embodiments, the porous semiconducting layer 14′ has an areal porosity of no greater than 80%. In some embodiments, the porous semiconducting layer 14′ has an areal porosity of no greater than 50%. Accordingly, the structural integrity of the porous semiconducting layer 14′ may be maintained following the porosity treatment process.

As shown in FIG. 3, following the porosity treatment process, the second semiconducting layer 14 is a porous semiconducting layer 14′. Thus, the monolithic growth stacks 10 are formed from a first semiconducting layer 12 and a third semiconducting layer 16 with a porous semiconducting layer 14′ provided between the first and third semiconducting layers 12, 16.

In the method according to the first embodiment, the third semiconducting layer 16 is further processed in order to define mesa structures for each LED precursor 1 of the LED array precursor. In the method of forming the first embodiment, the mesa structures are formed after the porosity treatment process. Of course, in other embodiments, the porosity treatment process could be performed after the formation of the mesa structures. As shown in FIG. 4, a plurality of monolithic growth stacks 10 are thus provided; one monolithic growth stack 10 for each LED precursor 1 of the LED array precursor.

As shown in FIG. 4, a plurality of monolithic growth stacks 10 are formed (indicated by the dashed line in FIG. 4). The plurality of monolithic growth stacks 10 are spaced apart from each other to form an array of monolithic growth stacks 10. The array of monolithic growth stacks 10 may be spaced apart across the first semiconducting layer 12 in a two-dimensional array. The plurality of monolithic growth stacks 10 may be spaced apart in a two-dimensional array with, for example, a square packing arrangement, or alternatively a hexagonal packing arrangement. The array of monolithic growth stacks 10 define the arrangement of the LED precursors in the LED array precursor. As such, it will be appreciated that methods according to the first embodiment may be used to fabricate a plurality of LED precursors arranged as an array across the first semiconducting layer 12.

As shown in FIG. 4, the monolithic growth stacks 10 of the first embodiment are formed by selectively removing a portion of the third semiconducting layer 16 from the growth surface 11 through a thickness of the third semiconducting layer 16. Accordingly, the growth surface 11 of each the monolithic growth stacks 10 comprises a mesa surface 30 of the third semiconducting layer 16 and a sidewall surface 32 of the third semiconducting layer 16 encircling the mesa surface 30. In FIG. 4 the third semiconducting layer 16 is selectively removed through its entire thickness (in a thickness direction normal to the growth surface 11) such that the growth surface 11 of the monolithic growth stack 10 comprises a surface of the porous semiconducting layer 14′. As such, the growth surface 11 of the monolithic growth stack 10 is shaped to define a mesa structure comprising the third semiconducting layer 16.

According to the method of the first embodiment, the selective removal process is performed prior to the heat treatment process. By performing the selective removal process prior to the heat treatment process, each of the mesa structures are provided with an additional volume of space between each mesa structure into which the third semiconducting layer 16 may strain relax during the heat treatment process. By providing the third semiconducting layer 16 with additional volume into which it can strain relax, the increase in the in-plane lattice constant of the mesa surface may be further increased. This in turn may reduce the strain formed when forming the active layer of the device, thereby improving the LED efficiency.

The mesa structures of the third semiconducting layer 16 may be shaped using a selective removal process. As such, portions of the third semiconducting layer 16 may be selectively removed to form the mesa structure shown in FIG. 4. For example, in FIG. 4 the growth surface 11 may be shaped using an etching process. In the etching process, a mesa-defining mask layer (not shown) may be deposited on the surface of third semiconducting layer 16. The mesa-defining mask layer may be configured to mask portions of the third semiconducting layer 16, which are intended to form the mesa surfaces 30 of the monolithic growth stacks 10. Un-masked portions of the third semiconducting layer 16 may then be selectively removed using an etchant. The etchant may etch away portions of the third semiconducting layer 16 to expose a surface of the porous semiconducting layer 14′. Of course, in other embodiments the etchant may not etch completely through the thickness of the third semiconducting layer to expose the porous semiconducting layer 14′ below. The mesa-defining mask layer may then be removed from the third semiconducting layer 16. By following the above process, the third semiconducting layer 16 may be shaped to provide a growth surface 11 comprising a mesa surface 30 and sidewall surfaces 32 formed by the third semiconducting layer 16.

The mesa surface 30 of each monolithic growth stack may have any shape desired. The shape of each mesa surface 30 may be determined by the shape of the mesa-defining mask layer. For example, the mesa surface 30 may have an elliptical shape, a triangular shape, a rectangular shape, or a hexagonal shape, or indeed any regular or irregular polygon. In some embodiments, each mesa surface 30 of the LED array precursor may have the same shape, thereby providing a relatively uniform array of monolithic growth stacks. Of course, in other embodiments, the mesa surfaces 30 may have different shapes.

The shape of the mesa surface 30 (i.e. the perimeter of the mesa surface 30) influences the shape of the sidewall surface 32 of the third semiconducting layer 16. For example, where the mesa surface 30 has an elliptical shape, the sidewall surface 32 may be provided as a single continuous surface. In other embodiments, for example where the mesa surface 30 has a regular or irregular polygon shape, there may be a plurality of sidewall surfaces 32, with one surface corresponding to each side of the regular or irregular polygon shape of the mesa surface 30.

In FIG. 4, the monolithic growth stacks 10 are shown with sidewall surfaces 32 which extend substantially perpendicular to the mesa surface 30 of the third semiconducting layer 16. In other embodiments, the sidewall surfaces of the mesa structures may be formed with a different angle inclination with respect to the mesa surface 30. That is to say, the sidewall surfaces 30 may be inclined. As such, the mesa structures formed by the third semiconducting layer 16 may have a trapezoidal cross-section in a plane normal to the mesa surface 30.

In the diagram of FIG. 4, the mesa structures may extend from the porous semiconducting layer 14′ by a distance of no greater than 100 μm. As such, in some embodiments the third semiconducting layer 16 may have a thickness in a direction normal to the mesa surface of no greater than 10 μm. In particular, in some embodiments, the mesa structures may extend from the porous semiconducting layer 14′ by a distance between 1 μm and 5 μm. Accordingly, in some embodiments the third semiconducting layer 16 may have a thickness in a direction normal to the mesa surface of around 1 μm to 5 μm.

In some embodiments of the disclosure, the mesa surfaces 30 may each have surface area dimensions of at least 1 μm×1 μm. Accordingly, for the mesa surfaces to fully relax, elastic deformation mechanisms will not be sufficient. That is to say, the propagation of misfit dislocations may provide a mechanism by which the mesa surfaces can strain relax to the desired lattice constant. Importantly, the presence of the porous semiconducting layer 14′ provides a region in which misfit dislocations preferentially propagate as half loop dislocations, thereby provided mesa structures with a reduced defect density. Further information on misfit dislocations at Group III-nitride heterointerfaces may be found in at least “Basal-plane Slip in InGaN/GaN Hetero Structures in the Presence of Threading Dislocations, Applied Physics Letters, vol. 90, 2007.

In some embodiments, the mesa surface 30 may each have surface area dimensions of no greater than 100 μm×100 μm.

Following the formation of the mesa structures in the third semiconducting layer 16, the layers of the monolithic growth stack are subjected to a heat treatment process in order to increase an in plane lattice constant of the growth surface of the monolithic growth stack 10.

The heat treatment process comprises heating the third semiconducting layer 16 of the monolithic growth stacks 10 to a strain relaxing temperature. The strain relaxing temperature causes the third semiconducting layer 16 to strain relax on the porous semiconducting layer 14′. Accordingly, following the heat treatment process the in-plane lattice constant of the growth surface 11 of the third semiconducting layer 16 will have increased.

The heat treatment process allows the third semiconducting layer 16 to strain relax such that the in-plane lattice constant of the third semiconducting layer 16 increases relative to the in-plane lattice constant of the as deposited third semiconducting layer 16.

In some embodiments the heat treatment process comprises heating the third semiconducting layer 16 from room temperature to a strain relaxing temperature. The strain relaxing temperature is a temperature sufficient to cause deformation of the compressively strained third semiconducting layer 16. For example, in some embodiments the strain relaxing temperature may be a temperature of at least 500° C. As such, the third semiconducting layer may be heated to a temperature wherein the third semiconducting layer releases the mechanical potential energy arising from its being compressed. Strain relaxation of the third semiconducting layer 16 may result in the formation of (misfit) dislocations towards the interface between the third semiconducting layer 16 and the second semiconducting layer 14. As a result of the heat treatment process, strain relaxation may occur via the propagation of misfit dislocation substantially across the c-plane of the porous semiconducting layer 14′ towards the interface, or at the interface between the porous semiconducting layer 14′ and the third semiconducting layer 16 (i.e. misfit dislocation glide in a c-plane), rather than in a direction transverse to the c-plane. The propagation of dislocations relieves at least some of the strain in the as-formed third semiconducting layer 16 such that the third semiconducting layer 16 strain relaxes. As such, the third semiconducting layer 16 strain relaxes through the propagation of misfit dislocations rather than through the propagation of threading dislocations. Consequently, the heat treatment process may reduce the strain in a region of the third semiconducting layer 16 above a narrow band in which the dislocations propagate. The presence of voids and dangling bonds in the porous semiconducting layer 14′ improves the propagation of misfit dislocations in the porous semiconducting layer 14′. As such, the third semiconducting layer 16 effectively strain relaxes (i.e. slides) on top of the porous semiconducting layer 14′. Further discussion of the propagation of misfit dislocations may be found in at least Mei et al., Basal-plane Slip in InGaN/GaN Hetero Structures in the Presence of Threading Dislocations, Applied Physics Letters, vol. 90, 2007, and Floro J. A. et al., Misfit Dislocation Formation in the AlGaN/GaN Heterointerface, Journal of Applied Physics, vol. 96, 2004.

It will be appreciated that in embodiments where the third semiconducting layer 16 forms a coherent interface with the second semiconducting layer 14, the heat treatment process causes the interface between the second and third semiconducting layers 14, 16 to no longer be a coherent interface.

The heat treatment process may be provided by any suitable method for annealing a material. For example, the heat treatment step may be provided by heating the third semiconducting layer 16 from room temperature up to a first strain relaxing temperature. The third semiconducting layer 16 may be held at the first strain relaxing temperature for a first time period. The third semiconducting layer 16 may then be cooled back to room temperature. The heat treatment step may be performed in air, for example on a hotplate, or in an oven. The heat treatment process may also be performed in a controlled atmosphere. In a controlled atmosphere, atmospheric compounds such as oxygen and water may be significantly reduced or excluded entirely. For example a controlled atmosphere may be a NH₃, Ar, or N₂atmosphere. In some embodiments, the heat treatment process may be formed under a controlled atmosphere comprising N₂and NH₃. Performing the heat treatment process under a controlled atmosphere may reduce or eliminate any undesirable chemical reactions from occurring on the surface of the third semiconducting layer 16 during the heat treatment process. For example, in some embodiments, the heat treatment process may be performed immediately prior to the process for forming the monolithic LED stack (i.e. in situ in a MOCVD reactor).

In some embodiments, the heat treatment process may heat the third semiconducting layer to a first strain relaxed temperature of at least 500° C. In some embodiments, the first strain relaxing temperature may be at least 800° C., 950° C., 1000° C., or 1050° C. The first time period may be at least 5 minutes. In some embodiments, the first time period may be at least: 10 minutes, 20 minutes, 30 minutes or 1 hour. For example, in some embodiments, a heat treatment step may comprise heating the third semiconducting layer 16 to 800° C. and holding the third semiconducting layer at this temperature for 1 hour followed by cooling to room temperature. At higher first strain relaxing temperatures, the first time period may be reduced.

By performing the heat treatment step following the porosity treatment process, the misfit dislocations which propagate at the interface between the third semiconducting layer 16, and the second semiconducting layer 14 are able to propagate more easily due to the presence of the pores in the second semiconducting layer 14.

Next, a monolithic LED stack 20 may be formed on the growth surface 11 of each of the monolithic growth stacks 10.

A monolithic LED stack 20 is formed on the growth surface 11 for each LED precursor 1. As shown in FIG. 5, the monolithic LED stack 20 covers the mesa surface 30 and the sidewall surfaces 32. The monolithic LED stack 20 comprises a plurality of layers, wherein each layer comprises a Group III-nitride. In some embodiments, the Group III-nitride layers comprise one or more of AlInGaN, AlGaN, InGaN, and GaN. In the first embodiment as shown in FIG. 5, the monolithic LED stack 20 comprises a fourth semiconducting layer 40, an active layer 22, and a p-type semiconducting layer 24.

As shown in FIG. 5, a fourth semiconducting layer 40 is formed on the growth surface 11 of the monolithic growth stack 10. Accordingly, the fourth semiconducting layer 40 covers the mesa surface 30 of the third semiconducting layer 16 and the sidewall surface 32 of the third semiconducting layer 16. As such, the fourth semiconducting layer 40 is formed on the third semiconducting layer 16 on an opposite side of the third semiconducting layer 16 to the porous semiconducting layer 14′.

The fourth semiconducting layer 40 may be formed on the growth surface 11 by any suitable method for the growth of Group III-nitrides. In the embodiment of FIG. 5, the fourth semiconducting layer 40 is formed monolithically over the growth surface 11 (i.e. an overgrowth method). As shown in FIG. 5, the fourth semiconducting layer 40 may be formed as a generally continuous layer covering substantially the entire growth surface 11.

As shown in FIG. 5, the fourth semiconducting layer 40 is formed on the growth surface 11 such that it forms generally inclined sidewall portions 42 extending from a mesa portion 44 of the fourth semiconducting layer 40 on the mesa surface 30 of the third semiconducting layer 16 towards the porous semiconducting layer 14′. The fourth semiconducting layer 40 also includes a bulk portion 46 which extend over the surface of the porous semiconducting layer 14′ between the inclined sidewall portions 42 of each monolithic LED precursor 1.

Accordingly, the fourth semiconducting layer 40 can be overgrown on the mesa structure of the third semiconducting layer 16 to provide a Group III-nitride semiconducting layer comprising a fourth semiconducting layer mesa surface 44 surrounded by an inclined sidewall surface 42. As such, the fourth semiconducting layer 40 may be overgrown on the mesa structure of the third semiconducting layer 16 to form a column having a regular trapezoidal cross-section in a plane normal to the mesa surface 30, wherein the fourth semiconducting layer mesa surface 44 forms a substantially flat upper surface of the trapezoidal cross-section. By regular trapezoidal cross-section it is meant that the column is narrower at the top than the bottom and it has a substantially flat upper surface with slopes at the sides. This may result in a frustroconical shape, or a frustropyramidal shape having three or more sides, typically six sides.

In some embodiments, for example as shown in FIG. 5, the sidewall portions 42 of the fourth semiconducting layer 40 have a substantially consistent angle (α) to a plane parallel to the mesa surface 30 of the growth surface 11. That is to say, the angle α between the sidewall surfaces of the fourth semiconducting layer 42 and a plane parallel to the mesa surface 30 do not change significantly. For example, in some embodiments the angle α may be at least 50 degrees at no greater than 70 degrees, and in some embodiments the angle α may be between 58 degrees and 64 degrees.

Accordingly, in some embodiments the sidewall portions of the fourth semiconducting layer 42 may be inclined with respect to the (0001) plane of the crystal structure of the third semiconducting layer 16. The inclined sidewalls may be generally orientated along the {1 1 0 1} or {1 1 0 2} planes of the wurtzite crystal and present reduced polarisation fields compared with C-plane surfaces (semi-polar surfaces).

Alternatively, for example as discussed in relation to the second embodiment, the fourth semiconducting layer 40 may be formed as a generally discontinuous layer which covers the mesa surface 30 and the sidewall surface 32 of each monolithic growth stack 10 and extends over a region of the porous semiconducting layer 14′ surrounding the mesa structure of the third semiconducting layer 16. The fourth semiconducting layer 40 may be deposited using any suitable process for the fabrication of Group III-nitride films, for example MOCVD, or MBE.

The fourth semiconducting layer 40 comprises a Group III-nitride. In the embodiment of FIG. 5, the fourth semiconducting layer 40 comprises GaN. In some embodiments, the fourth semiconducting layer 40 may be n-type doped. The fourth semiconducting layer 40 may be n-type doped using a suitable dopant, for example, Si, or Ge. In the embodiment of FIG. 5, the fourth semiconducting layer 40 is not intentionally doped. As such, the fourth semiconducting layer 40 may be a (substantially) undoped layer. By substantially undoped, it is understood that the Group III-nitride does not include any significant quantity of dopant elements, whilst appreciating that some impurities may be present as a result of the fabrication process. By forming the fourth semiconducting layer 40 from an undoped semiconductor, the flow of charge carriers through the LED precursor may be more efficiently confined in the mesa structure.

By growing the fourth semiconducting layer 40 on the growth surface provided by the third semiconducting layer 16, the fourth semiconducting layer 40 may have a crystal structure which is coherent with the crystal structure of the third semiconducting layer 16. For example, where the mesa surface 30 of the third semiconducting layer 16 is aligned with the (0001) plane of a Group III-nitride, the fourth semiconducting layer 40 formed on the mesa surface 30 may form a coherent interface and have a similar (0001) crystal orientation. As such, in-plane lattice constant of the fourth semiconducting layer 40 on the mesa surface 30 may correspond to the in-plane lattice constant of the third semiconducting layer 16 at the mesa surface 30.

As shown in FIG. 5, an active layer 22 may then be formed on the fourth semiconducting layer 40. The active layer 22 is configured to generate light of a first wavelength as part of the monolithic LED stack 20.

The active layer 22 is configured to generate light of a first wavelength as part of the monolithic LED stack 20. In the embodiment of FIG. 5, the active layer 22 may comprise one or more quantum well layers (not shown). As such, the active layer 22 may be a multiple quantum well layer. The quantum well layers within the active layer 22 may each comprise a Group III-nitride semiconductor, for example a Group III-nitride alloy comprising In. In the embodiment of FIG. 5, the active layer 22 comprises alternating layers of GaN and In_ZGa_1-ZZ, where 0<Z≤1. In particular, in some embodiments the active layer may comprise In_ZGa_1-ZN layers where 0.2≤Z≤0.5. As such, the active layer 22 of the monolithic LED stack may be configured to output light having a wave length of at least 525 nm. The thickness and In content of the quantum well layers may be controlled in order to control the wavelength of the light generated by the active layer 22. The active layer 22 may be formed as a continuous layer covering a substantial portion of the exposed growth surface. The active layer 22 may be deposited using any suitable process for the fabrication of Group III-nitride thin films, for example MOCVD or MBE.

In some embodiments, the active layer 22 may comprise a strain interface layer (not shown). The strain interface layer may be formed between the growth surface 11 and the multiple quantum well structure, as is known in the art.

The deposition of the active layer 22 on the fourth semiconductor layer 40 may occur with a relatively high deposition rate on the mesa portion of the fourth semiconducting layer 44, and with a significantly lower deposition rate on the inclined sidewall portions of the fourth semiconducting layer 42. This effect results from the different crystal plane alignment of the various surfaces, resulting in a thicker active layer 22 over the mesa surface 30 than on the inclined sidewall portions 42. This effect is described in more detail in GB1811190.6.

Accordingly, the active layer 22 may include an active layer mesa portion 23 which extends over the mesa portion 44 of the fourth semiconducting layer 40. The active layer 22 may also include active layer sidewall portions 28 which extend over the sidewall portions 42 of the fourth semiconducting layer 40. The active layer sidewall portions 28 encircle the active layer mesa portion 23 and extend from the active layer mesa portion 23 towards the porous semiconducting layer 14′. As such, the active layer sidewall portions 28 are generally aligned with the inclined sidewall portions of the fourth semiconducting layer 42. The active layer 22 may also include active layer bulk portions 29 which extend over the bulk portions 46 of the fourth semiconducting layer 40 between the active layer sidewall portions 28 of each monolithic LED precursor 1.

It will be appreciated that various methodologies for forming a monolithic LED stack 20 comprising an active layer 22 are known to the skilled person. Accordingly, it will be appreciated that the methodology described in relation to FIGS. 1 to 5 is only one example of a possible methodology of forming a monolithic LED stack 20. For example, in the embodiment of FIG. 5 the active layer 22 may have a thickness in a direction generally normal to the growth surface of at least 30 nm and no more than 150 nm. In some embodiments, the active layer 22 may have a thickness in the thickness direction of at least 40 nm and not greater than 60 nm.

Further layers of the monolithic LED stack 20 may then be deposited on the active layer 22 on an opposite side of the active layer 22 to the monolithic growth stack 10. For example, as shown in FIG. 5 the p-type semiconducting layer 24 is subsequently formed on the active layer 22.

As shown in FIG. 5 a p-type semiconducting layer 24 is provided on the active layer 22. The p-type semiconducting layer 24 comprises a Group III-nitride. The p-type semiconducting layer 24 is doped with a suitable electron acceptor, for example Mg. The p-type semiconducting layer 24 may be formed as a substantially continuous layer covering a substantial portion (e.g. all) of the exposed surface of the active layer 24. The p-type semiconducting layer may be formed using any suitable process for the fabrication of Group III-nitride thin films, for example MOCVD or MBE.

As shown in FIG. 5, the p-type semiconducting layer 24 is formed on the exposed surface of the active layer 22. As such, in the embodiment of FIG. 5, the p-type semiconducting layer 24 is a generally continuous layer. Of course, in other embodiments, the p-type semiconducting layer 24 may be formed as a discontinuous layer.

The p-type semiconducting layer 24 may have a thickness (in a thickness direction normal to the mesa surface 30) of at least: 50 nm, 60 nm, 70 nm, 80 nm or 100 nm. Further, the p-type semiconducting layer 24 may have a thickness of no greater than: 300 nm, 250 nm or 200 nm. For example, in the embodiment of FIG. 5 the p-type semiconducting layer 24 may have a thickness of around 100 nm.

The p-type semiconducting layer 24 for each LED precursor may comprise a p-type mesa portion 25 and one or more p-type sidewall portions 26. The p-type mesa portion 25 may be substantially aligned with the mesa surface 30 of the monolithic growth stack 10. The p-type sidewall portion 26 encircles the p-type mesa portion 25 and extends from the p-type mesa portion 25 towards the porous semiconducting layer 14′. As such, the p-type sidewall portions 26 are generally aligned with the inclined sidewall portions of the fourth semiconducting layer 42. The p-type semiconducting layer 24 may also include a p-type bulk portion 27 which extends over the active layer bulk portion 29 between the p-type sidewall portions 26 of each monolithic LED precursor 1.

Accordingly, FIG. 5 shows an embodiment of an LED array precursor according to this disclosure. The LED array precursor may be fabricated according to the method set out in the described above. In accordance with the definition of the term precursor in this disclosure, it will be appreciated that the LED array precursor of FIG. 5 may be subjected to further fabrication steps in order to form electrical contacts to each of the LED precursors. Accordingly, it will be appreciated that the LED array precursor may be subjected to further fabrication steps in order to provide an LED and/or an LED array.

For example, in order to provide for the independent control of one of the monolithic LED precursors according to the first embodiment, a portion of at least the p-type mesa portion 25, or the p-type sidewall portions 26 encircling the mesa surface 30 may be selectively removed. Thus, the p-type mesa portion 25 of each monolithic LED precursor 1 may be provided with electrical power (i.e. current/voltage) independently of other p-type mesa portions 25. Such a selective removal process may be performed as part of the process of forming electrical contacts to the monolithic LED precursors 1.

In particular, in some embodiments the monolithic growth stacks 10 may be sized in order to provide a micro LED precursor and/or a micro LED array precursor. For example, in some embodiments the monolithic LED stack 20 of each micro LED precursor may have a footprint on the first semiconducting layer 12 of less than 100 μm×100 μm. As such, each LED precursor may be a micro LED precursor wherein the monolithic LED stack 20 has a surface area dimension in a plane aligned with the first semiconducting layer 12 of less than 100 μm×100 μm.

In accordance with the methodology set out with reference to FIGS. 1 to 5 a LED precursor 1 is provided. As such, an embodiment of an LED precursor 1 according to this disclosure is shown in FIG. 5. The LED precursor 1 of FIG. 5 comprises a monolithic growth stack 10 and a monolithic LED stack 20. The monolithic growth stack 10 comprises a first semiconducting layer 12, a second semiconducting layer 14, and a third semiconducting layer 16. The monolithic LED stack comprises an active layer 22 and p-type semiconducting layer 24. Each of the layers of the monolithic growth stack 10 and monolithic LED stack 20 may have properties in accordance with the discussion of the method of forming the LED precursor 1 described above.

According to a second embodiment of the disclosure, a LED precursor 1 is provided. In some embodiments, a plurality of LED precursors 1 arranged to form a LED array precursor may be provided. For example, a LED array precursor comprising a plurality of LED precursors according to the second embodiment may be formed using a methodology as shown in FIGS. 3, 6, and 7.

The method according to the second embodiment of the disclosure comprises forming a monolithic growth stack 10 and a monolithic LED stack 20 for each LED precursor 1. Similar to the first embodiment, the monolithic LED stacks 20 are formed on a growth surface 11 of a respective monolithic growth stack 10. Like features of the first, second embodiments have corresponding reference numerals. FIG. 3 shows a diagram of the layers used to form the monolithic growth stacks 10 of the second embodiment. As shown in FIG. 3, the monolithic growth stacks 10 are formed form a first semiconducting layer 12, a porous semiconducting layer 14′ and a third semiconducting layer 16. As discussed previously, the porous semiconducting layer 14′ in FIG. 3 has been formed from a second semiconducting layer 14 which has been subjected to a porosity treatment process.

Similar to the method of the first embodiment, the third semiconducting layer 16 is subjected to a selective removal process prior to the heat treatment process in order to form a plurality of mesa structures. Each mesa structure formed using the selective removal step may be used to define a LED precursor of the LED array precursor. The mesa structures may be arranged in a two-dimensional array as discussed for the first embodiment above. The method of the second embodiment differs from the method of the first embodiment, in that the selective removal step removes a portion of the third semiconducting layer 16 and a portion of the porous semiconducting layer 14′ encircling each of the mesa structures.

For example, as shown in FIG. 6, the selective removal process has selectively removed a portion of the third semiconducting layer 16 from the growth surface 11 through a thickness (in a thickness direction normal to the mesa surface 30) of the third semiconducting layer 16 and through a thickness of the porous semiconducting layer 14′. Accordingly, the growth surface 11 of each of the monolithic growth stacks 10 comprises a mesa surface of the third semiconducting layer 16, a sidewall surface 32 of the third semiconducting layer 16 and a porous sidewall surface 34 of the porous semiconducting layer 14′. Accordingly, as shown in FIG. 6 the third semiconducting layer 16 and the porous semiconducting layer 14′ are selectively removed through their entire thicknesses such that the first surface 13 of the first semiconducting layer 12 is exposed between each of the mesa structures. The selective removal process may be performed using an etchant in a similar manner to the selective removal process discussed above for the first embodiment. In some embodiments, the selective removal process may also selectively remove portions of the first semiconducting layer 12. As such, the mesa structure may be defined by the monolithic growth stack 10 (indicated in dashed lines in FIG. 6).

Similar to the first embodiment, the shape of the mesa surfaces 30 in the third embodiment may have any suitable shape. Furthermore, the sidewall surfaces 32 and the porous sidewall surfaces 34 may be formed with any angle of inclination with respect to the mesa surfaces 30. As such, the mesa structures formed by the third semiconducting layer 16 and the porous semiconducting layer 14′ may have a trapezoidal cross-section in a plane normal to the mesa surface 30.

Following the formation of the mesa structures, a heat treatment process is performed. The heat treatment process may be performed substantially as described for the first embodiment. The heat treatment process allows the third semiconducting layer 16 to strain relax wherein an in-plane lattice constant of the growth surface increases. Following the strain relaxation, the interface between the third semiconducting layer 16 and the porous semiconducting layer 14′ is no longer coherent.

Next, a monolithic LED stack 20 may be formed on the growth surface 11 of each of the monolithic growth stacks 10.

In some embodiments, the monolithic LED stacks 20 may be grown as substantially continuous layers, for example as described above in relation to the first embodiment.

In other embodiments, for example as shown in the second embodiment, the monolithic growth stacks 20 may be formed as generally discontinuous layers.

As shown in FIG. 6, following the formation of the monolithic growth stacks 10, a masking layer 50 is provided over the exposed surface of the porous semiconducting layer 14′. The masking layer 50 is configured to prevent, or significantly reduce, growth of the fourth semiconducting layer 40 nucleating on (i.e. starting on) the masking layer 50. The masking layer is configured to restrict the growth surface 11 of each monolithic growth stack 10 to the mesa surface 30 and the sidewall surfaces of the monolithic growth stack 10. As such, the masking layer 50 in the second embodiment is configured to reduce, or prevent, the formation of the bulk portions 46 of the fourth semiconducting layer 40. Accordingly, the use of a masking layer 50 is one example of a method of forming discontinuous monolithic LED stacks 20.

In some embodiments, the masking layer 50 may be formed from SiO₂, SiN_X, or any other suitable masking material such as a dielectric material (i.e. a dielectric layer). In some embodiments, the masking layer 50 may have a thickness in a direction normal to the mesa surface 30 of at least 50 nm. In some embodiments, a thickness in the direction normal to the mesa surface 30 of the masking layer 50 may be no greater than 500 nm.

Next, the monolithic Led stacks 20 may be formed on the (discontinuous) growth surface 11 of the array of monolithic growth stacks 10. The resulting structure is shown in FIG. 7. The fourth semiconducting layer 40 is formed on the growth surface 11 such that it forms a generally inclined sidewall portion 42 extending from a mesa portion 44 of the fourth semiconducting layer 40 on the mesa surface 30 of the third semiconducting layer 16 towards the porous semiconducting layer 14′. The fourth semiconducting layer 40 does not grow, or grows at a significantly reduced rate on the masking layer 50. It will be appreciated that the regions of the fourth semiconducting layer