Aspects of the present relate to solid-state lighting devices including light-emitting diodes (LEDs) and more particularly to a semi-transparent metallic layer deposited on an LED chip that can dim a light output of the LED chip. The metallic layer can be semi-transparent to wavelengths of light emitted by the LED chip. Standard sapphire alternatives struggle to meet binning requirements as the brightness is often too high. The present disclosure provides a solution, as an existing chip platform can include a titanium or other metal layer in place of etching passivation and texturing in order to provide chips with a range of brightnesses using the same chip platform. The thickness of the metal layer can be modified to provide different dimming levels, thus allowing a single LED chip platform to meet a variety of brightness requirements. Titanium or platinum metal layers can be used since the metal layer adheres well to the passivation layers, and it can withstand gold etchants while still possessing light blocking capabilities.

FIG. 1 is a generalized cross-section of an LED chip 10 that embodies a vertical chip structure according to principles of the present disclosure. The LED chip 10 includes an active LED structure 12 formed on a carrier submount 14. The active LED structure 12 generally refers to portions of the LED chip 10 that include semiconductor layers, such as epitaxial semiconductor layers, that form a structure that generates light when electrically activated. The active LED structure 12 is formed on and supported by the carrier submount 14 that can be made of many different materials, with a suitable material being silicon, or doped silicon. In certain embodiments, the carrier submount 14 comprises an electrically conductive material such that the carrier submount 14 is part of electrically conductive connections to the active LED structure 12. The active LED structure 12 may generally comprise a p-type layer 16, an n-type layer 18, and an active layer 20 arranged between the p-type layer 16 and the n-type layer 18. The active LED structure 12 may include many additional layers such as, but not limited to, buffer layers, nucleation layers, super lattice structures, un-doped layers, cladding layers, contact layers, current-spreading layers, and light extraction layers and elements. Additionally, the active layer 20 may comprise a single quantum well, a multiple quantum well, a double heterostructure, or super lattice structures. In FIG. 1, the p-type layer 16 is arranged between the active layer 20 and the carrier submount 14 such that the p-type layer 16 is closer to the carrier submount 14 than the n-type layer 18. The active LED structure 12 may initially be formed by epitaxially growing or depositing the n-type layer 18, the active layer 20, and the p-type layer 16 sequentially on a growth substrate. The active LED structure 12 may then be flipped and bonded to the carrier submount 14 by way of one or more bond metals 22 and the growth substrate is removed. In this manner, a top surface 18′ of the n-type layer 18 forms a primary light extracting face of the LED chip 10. In certain embodiments, the top surface 18′ may comprise a textured or patterned surface for improving light extraction. In other embodiments, the doping order may be reversed such that the n-type layer 18 is arranged between the active layer 20 and the carrier submount 14. In an embodiment, an outer layer 50 applied over top surface 18′ of the n-type layer 18 to cover and protect the top surface 18′. In an embodiment, the outer layer 50 can be a neutral dielectric material such as SiN, SiO₂, or Al₂O₃or other suitable passivating materials.

The LED chip 10 may include a first reflective layer 24 provided on the p-type layer 16. In certain embodiments, a current spreading layer 26 may be provided between the p-type layer 16 and the first reflective layer 24. The current spreading layer 26 may include a thin layer of a transparent conductive oxide such as indium tin oxide (ITO) or a thin metal layer such as Platinum (Pt), although other materials may be used. The first reflective layer 24 may comprise many different materials and preferably comprises a material that presents an index of refraction step with the material of the active LED structure 12 to promote total internal reflection (TIR) of light generated from the active LED structure 12. Light that experiences TIR is redirected without experiencing absorption or loss and can thereby contribute to useful or desired LED chip emission. In certain embodiments, the first reflective layer 24 comprises a material with an index of refraction lower than the index of refraction of the active LED structure 12 material. The first reflective layer 24 may comprise many different materials, with some having an index of refraction less than 2.3, while others can have an index of refraction less than 2.15, less than 2.0, and less than 1.5. In certain embodiments, the first reflective layer 24 comprises a dielectric material, such as silicon dioxide (SiO₂) and/or silicon nitride (SiN). It is understood that many dielectric materials can be used such as SiN, SiN_x, Si₃N₄, Si, germanium (Ge), SiO₂, SiOx, titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), ITO, magnesium oxide (MgOx), zinc oxide (ZnO), and combinations thereof. In certain embodiments, the first reflective layer 24 may include multiple alternating layers of different dielectric materials, e.g., alternating layers of SiO₂and SiN that symmetrically repeat or are asymmetrically arranged. Some Group III nitride materials such as GaN can have an index of refraction of approximately 2.4, and SiO₂can have an index of refraction of approximately 1.48, and SiN can have an index of refraction of approximately 1.9. Embodiments with the active LED structure 12 comprising GaN and the first reflective layer 24 comprising SiO₂may form a sufficient index of refraction step between the two to allow for efficient TIR of light. The first reflective layer 24 may have different thicknesses depending on the type of materials used, with some embodiments having a thickness of at least 0.2 microns (μm). In some embodiments, the first reflective layer 24 can have a thickness in the range of 0.2 μm to 0.7 μm, while in some embodiments the thickness can be approximately 0.5 μm.

The LED chip 10 may further include a second reflective layer 28 that is on the first reflective layer 24 such that the first reflective layer 24 is arranged between the active LED structure 12 and the second reflective layer 28. The second reflective layer 28 may include a metal layer that is configured to reflect light from the active LED structure 12 that may pass through the first reflective layer 24. The second reflective layer 28 may comprise many different materials such as Ag, gold (Au), Al, nickel (Ni), titanium (Ti) or combinations thereof. The second reflective layer 28 may have different thicknesses depending on the type of materials used, with some embodiments having a thickness of at least 0.1 μm, or in a range including 0.1 μm to 0.7 μm, or in a range including 0.1 um to 0.5 um, or in a range including 0.1 μm to 0.3 μm. As illustrated, the second reflective layer 28 may include or form one or more reflective layer interconnects 30 that provide an electrically conductive path through the first reflective layer 24. In this manner, the one or more reflective layer interconnects 30 may extend through an entire thickness of the first reflective layer 24. In certain embodiments, the second reflective layer 28 is a metal reflective layer and the reflective layer interconnects 30 comprise reflective layer metal vias. Accordingly, the first reflective layer 24, the second reflective layer 28, and the reflective layer interconnects 30 form a reflective structure of the LED chip 10 that is on the p-type layer 16. As such, the reflective structure may comprise a dielectric reflective layer and a metal reflective layer as disclosed herein. In certain embodiments, the reflective layer interconnects 30 comprise the same material as the second reflective layer 28 and are formed at the same time as the second reflective layer 28. In other embodiments, the reflective layer interconnects 30 may comprise a different material than the second reflective layer 28. Certain embodiments may also comprise an adhesion layer 32 that is positioned at one or more interfaces between the first reflective layer 24 and the second reflective layer 28 and/or interfaces between the first reflective layer 24 and the current spreading layer 26 to promote improved adhesion therebetween. Many different materials can be used for the adhesion layer 32, such as titanium oxide (TiO, TiO₂), titanium oxynitride (TiON, Ti_xO_yN), tantalum oxide (TaO, Ta₂O₅), tantalum oxynitride (TaON), aluminum oxide (AlO, Al_xO_y) or combinations thereof, with a preferred material being TiON, AlO, or AlxOy. In certain embodiments, the adhesion layer comprises Al_xO_y, where 1≤x≤4 and 1≤y≤6. In certain embodiments, the adhesion layer comprises Al_xO_y, where x=2 and y=3, or Al₂O₃. The adhesion layer 32 may be deposited by electron beam deposition that may provide a smooth, dense, and continuous layer without notable variations in surface morphology. The adhesion layer 32 may also be deposited by sputtering, chemical vapor deposition, or plasma enhanced chemical vapor deposition.

The LED chip 10 may also comprise a barrier layer 34 on the second reflective layer 28 to prevent migration of material of the second reflective layer 28, such as Ag, to other layers. Preventing this migration helps the LED chip 10 maintain efficient operation throughout its lifetime. The barrier layer 34 may comprise an electrically conductive material, with suitable materials including but not limited Ti, Pt, Ni, Au, tungsten (W), and combinations or alloys thereof. In certain embodiments, the barrier layer 34 is arranged to laterally extend beyond portions of the active LED structure 12, or a peripheral border of the active LED structure 12 in order to provide an electrical connection with a p-contact 36. In this regard, an electrical path between the p-contact 36 and the p-type layer 16 may include the barrier layer 34, the second reflective layer 28, and the reflective layer interconnects 30. In other embodiments, the polarity may be reversed such that the p-contact 36 is replaced with an n-contact that is electrically coupled to the n-type layer 18 and electrical connections to the p-type layer 16 are made through the carrier submount 14. A passivation layer 38 is included on the barrier layer 34 as well as any portions of the second reflective layer 28 that may be uncovered by the barrier layer 34. The passivation layer 38 protects and provides electrical insulation for the LED chip 10 and can comprise many different materials, such as a dielectric material including but not limited to silicon nitride. In certain embodiments, the passivation layer 38 is a single layer, and in other embodiments, the passivation layer 38 comprises a plurality of layers. In certain embodiments, the passivation layer 38 may include one or more metal-containing interlayers arranged or embedded therein that may function as a crack stop layer for any cracks that may propagate through the passivation layer 38 as well as an additional light reflective layer.

In FIG. 1, the active LED structure 12 forms a first opening 40 or recess that extends through the p-type layer 16, the active layer 20, and a portion of the n-type layer 18. The first opening 40 may be formed by a subtractive material process, such as etching, that is applied to the active LED structure 12 before bonding with the carrier submount 14. As used herein, the first opening may also be referred to as an active LED structure opening. As illustrated, a portion of the first reflective layer 24, and adhesion layer 32, is arranged to cover sidewall surfaces of the p-type layer 16, the active layer 20, and the n-type layer 18 within the first opening 40. The passivation layer 38 extends along the first reflective layer 24 in the first opening 40 and is arranged on a surface of the n-type layer 18. The LED chip 10 further includes an n-contact metal layer 42 that is arranged on the passivation layer 38 and across the LED chip 10. At the first opening 40, the n-contact metal layer 42 extends into the first opening 40 to form an n-contact interconnect 44, which may be referred to as an n-contact via. In this manner, the first opening 40 may be defined where portions of the n-contact metal layer 42, the n-contact interconnect 44, the passivation layer 38, and the first reflective layer 24 extend into the active LED structure 12. As such, the n-contact metal layer 42 and the n-contact interconnect 44 may be integrally formed to provide an electrical connection to the n-type layer 18 through the first opening 40. In other embodiments, the n-contact metal layer 42 and the n-contact interconnect 44 may be separately formed and may comprise the same or different materials. In certain embodiments, the n-contact metal layer 42 and the n-contact interconnect 44 comprise a single layer or a plurality of layers that include conductive metals, such as one or more of Al, Ti, and alloys thereof.

As illustrated, the p-contact 36 may be formed on the barrier layer 34, and one or more top passivation layers 46-1, 46-2 may be provided on one or more top or side surfaces of the n-type layer 18 for additional electrical insulation. In FIG. 1, the top passivation layer 46-2 is arranged to cover mesa sidewalls 12′ of the active LED structure 12. The top passivation layers 46-1, 46-2 may comprise separate layers of a continuous layer of dielectric material, such as silicon nitride. During fabrication of the mesa for the active LED structure 12, an etching step is applied to the active LED structure 12 from the n-type layer 18. The etching step effectively forms the mesa sidewalls 12′ with sloped surfaces along the perimeter of the active LED structure 12.

FIG. 2 is a cross-section of an LED chip 11 that is similar to the LED chip 10 of FIG. 1