1.

The sixth transistor T6 may be a p-type transistor and may include a polycrystalline semiconductor. The sixth transistor T6 may transmit the driving current output by the first transistor T1 to the light emitting diode LED. A gate electrode of the sixth transistor T6 may be connected to the light emitting control line GL5, a first electrode of the sixth transistor T6 may be connected to the second electrode of the first transistor T1, and a second electrode of the sixth transistor T6 may be connected to the anode of the light emitting diode LED.

The seventh transistor T7 may be a p-type transistor and may include a polycrystalline semiconductor. The seventh transistor T7 may initialize the anode of the light emitting diode LED. A gate electrode of the seventh transistor T7 may be connected to the bypass control line GL4, a first electrode of the seventh transistor T7 may be connected to the anode of the light emitting diode LED, and a second electrode of the seventh transistor T7 may be connected to the second initialization voltage line VL4. When the seventh transistor T7 is turned on by a gate-on voltage (or a low voltage) of the bypass signal GB, the second initialization voltage V_INT2may be applied to the anode of the light emitting diode LED.

The eighth transistor T8 may be a p-type transistor and may include a polycrystalline semiconductor. A gate electrode of the eighth transistor T8 may be connected to the bypass control line GL4, a first electrode of the eighth transistor T8 may be connected to the reference voltage line VL2, and a second electrode of the eighth transistor T8 may be connected to the first electrode of the first transistor T1. When the eighth transistor T8 is turned on by a gate-on voltage (or a low voltage) of the bypass signal GB, the reference voltage V_EHmay be applied to the first electrode of the first transistor T1.

A second electrode of the storage capacitor C_STmay be connected to the driving voltage line VL1. A cathode of the light emitting diode LED may be connected to the common voltage line VL5 for transmitting the common voltage EL_VSS.

A parasitic capacitor C_AKmay be disposed between the data line DL and the anode of the light emitting diode LED. When the display device is driven at a high rate (e.g., a frequency of about 240 Hz), a lower region (e.g., a region of R2 in FIG. 1) of the display panel may be a blank frame while an upper region (e.g., a region of R1 in FIG. 1) of the display panel is an active frame. The bypass signal GB is applied to the pixel circuit of the upper region and the pixel circuit of the lower region so the second initialization voltage V_INT2may be applied to the anode of the light emitting diode LED of the lower region. When the data voltage V_DATAfor the upper region is changed, the second initialization voltage V_INT2applied to the anode of the light emitting diode LED of the lower region is changed by the parasitic capacitance C_AKbetween the data line DL and the anode, and stains (changes of luminance) may be generated in the lower region. The generation of stains may be reduced by reducing capacity of the parasitic capacitance C_AK, and an embodiment for reducing the capacity of the parasitic capacitance C_AKwill be described in a later portion of the present specification.

In addition, differing from the shown embodiment, the third transistor T3 and the fourth transistor T4 may include polycrystalline semiconductors and may be p-type transistors. In the shown embodiment, the pixel PX includes eight transistors T1 to T8 and one storage capacitor C_ST, and a number of the transistors, a number of the capacitors, and their connections are modifiable in many ways.

FIG. 3 shows atop plan view of pixels disposed in a display area of alight emitting display device according to an embodiment, FIG. 4 shows a cross-sectional view with respect to a line A-A′ of FIG. 3, and FIG. 5 shows a cross-sectional view with respect to a line B-B′ of FIG. 3. To avoid complexity of the drawings, constitutional elements for indicating characteristics of the present embodiment from among the constitutional elements described with reference to FIG. 2 are generally shown.

FIG. 3 shows pixels PXa, PXb, and PXc disposed in the display area DA of the display panel 10. Three pixels are shown, and the pixels PXa, PXb, and PXc may be regularly disposed in a matrix direction in the display area DA. The pixels PXa, PXb, and PXc may include a first pixel PXa, a second pixel PXb, and a third pixel PXc. The first pixel PXa, the second pixel PXb, and the third pixel PXc may display different colors and may display one of primary colors. For example, one of the first pixel PXa, the second pixel PXb, and the third pixel PXc may display a red color, another may display a green color, and the other may display a blue color. For example, the first pixel PXa may display the red color, the second pixel PXb may display the green color, and the third pixel PXc may display the blue color. A region of the third pixel PXc may be wider than a region of the first pixel PXa or the second pixel PXb.

The first pixel PXa, the second pixel PXb, and the third pixel PXc may be disposed to be evenly distributed. For example, the first pixel PXa and the second pixel PXb may be alternately and repeatedly disposed in the second direction y. The first and second pixels PXa and PXb and the third pixel PXc may be alternately and repeatedly disposed in the first direction x. Disposal of the pixels PXa, PXb, and PXc are changeable in various ways.

The first pixel PXa, the second pixel PXb, and the third pixel PXc may respectively include a first pixel electrode E1a, a second pixel electrode E1b, and a third pixel electrode E1c. A region of the third pixel electrode E1c may be wider than the region of the first pixel electrode E1a or the second pixel electrode E1b. The third pixel electrode E1c may include at least one first opening OP1 substantially extending in the second direction. The third pixel electrode E1c may include at least one second opening OP2 substantially extending in the first direction. The first opening OP1 may/may not be connected to the second opening OP2. Three first openings OP1 and two second openings OP2 are formed according to an embodiment, and the number of the first openings OP1 and the second openings OP2 is modifiable in various ways.

The first pixel PXa, the second pixel PXb, and the third pixel PXc may respectively include a first emission layer ELa, a second emission layer ELb, and a third emission layer ELc. The third emission layer ELc may include portions ELc1 to ELc6 separated by the first opening OP1 and the second opening OP2.

The data lines DLa, DLb, and DLc may be positioned to be near the pixels PXa, PXb, and PXc or partially overlap them. The data lines DLa, DLb, and DLc may substantially extend in the second direction y. The data lines DLa, DLb, and DLc may include a first data line DLa for transmitting the data voltage to the first pixel PXa, a second data line DLb for transmitting the data voltage to the second pixel PXb, and a third data line DLc for transmitting the data voltage to the third pixel PXc. The third data line DLc may traverse the third pixel electrode E1c and may extend further because of a spatial restriction for disposing the pixels PXa, PXb, and PXc and wires. By this, coupling between the third data line DLc and the third pixel electrode E1c may be a problem. To solve the problem, the first opening OP1 may be formed in the third pixel electrode E1c to overlap the third data line DLc, and the region where the third pixel electrode E1c overlaps the third data line DLc may be reduced. Accordingly, the parasitic capacitance C_AKbetween the third pixel electrode E1c and the third data line DLc may be reduced, and image quality defects such as generation of stains caused by the parasitic capacitance C_AKmay be improved. For example, when the first opening OP1 is formed in the third pixel electrode E1c as shown above, capacitance between the third pixel electrode E1c and the third data line DLc may be reduced to about ½ to about ⅓, compared to the case in which the first opening OP1 is not formed therein. It may be more advantageous in reducing the parasitic capacitance C_AKthat the width of the first opening OP1 is greater than the width of the third data line DLc, and the former may be substantially equal to or less than the latter.

The driving voltage line VL1 may substantially extend in the second direction y, and it may overlap the first pixel PXa and the second pixel PXb or may overlap the third pixel PXc. Voltage lines such as the reference voltage line VL2, the first initialization voltage line VL3, the second initialization voltage line VL4, or the common voltage line VL5 may substantially extend in the second direction y, and may or may not overlap the pixels PXa, PXb, and PXc.

Referring to FIG. 3, FIG. 4, and FIG. 5, the display panel 10 may include a substrate 110 and layers and parts positioned on the substrate 110. In detail, a first insulating layer IL1 may be positioned on the substrate 110. Although not shown, transistors, capacitors, and signal lines configuring a pixel circuit for driving the pixels PXa, PXb, and PXc may be positioned between the substrate 110 and the first insulating layer IL1, which will be described in a later part of the present specification.

The data lines DLa, DLb, and DLc may be positioned on the first insulating layer IL1. The driving voltage line VL1 may be positioned on the first insulating layer IL1, and the reference voltage line VL2, the first initialization voltage line VL3, the second initialization voltage line VL4, or the common voltage line VL5 may be positioned thereon.

A second insulating layer IL2 may be positioned on the data lines DLa, DLb, and DLc and the voltage lines VL1 to VL5.

The first pixel electrode E1a, the second pixel electrode E1b, and the third pixel electrode E1c may be positioned on the second insulating layer IL2. The first pixel electrode E1a may be the anode of the light emitting diode LED configuring the first pixel PXa. The second pixel electrode E1b may be the anode of the light emitting diode LED configuring the second pixel PXb. The third pixel electrode E1c may be the anode of the light emitting diode LED configuring the third pixel PXc. The third pixel electrode E1c may include the openings OP1 and OP2. The openings OP1 and OP2 may respectively have a slit shape and may penetrate the third pixel electrode E1c in a thickness direction (or the third direction z). The openings OP1 and OP2 may include a first opening OP1 substantially extending in the second direction y and a second opening OP2 substantially extending in the first direction x. The first opening OP1 may extend to be parallel to the third data line DLc and overlap the same. Accordingly, the region in which the third pixel electrode E1c overlaps the third data line DLc may be reduced, and the coupling and the parasitic capacitance C_AKbetween the third pixel electrode E1c and the third data line DLc may be reduced. To further reduce the parasitic capacitance C_AK, the width of the first opening OP1 may be greater than the width of the third data line DLc, and the third data line DLc may be positioned in the first direction x in the first opening OP1.

The first opening OP1 and the second opening OP2 may discharge gas generated by the second insulating layer IL2. The second insulating layer IL2 may be formed by coating an organic insulating material including an organic solvent, an initiator, and a binder and curing the same. A material remaining in the second insulating layer IL2 or a decomposed material may be discharged as a gas in a subsequent process after the second insulating layer IL2 is formed or during use of the display device. This phenomenon will be referred to as outgassing. The discharged gas (particularly, after manufacturing the display panel) may be provided to the pixels PXa, PXb, and PXc to denaturalize or degrade the emission layers ELa, ELb, and ELc of the pixels PXa, PXb, and PXc or the common electrode E2 and reduce light emitting regions of the pixels PXa, PXb, and PXc, which will be referred to as generation of shrinkage. The third pixel electrode E1c may be formed to be a relatively wide area, and the gas generated in the region overlapping the third pixel electrode E1c may not be easily discharged when the display panel is manufactured. As the openings OP1 and OP2 are formed in the third pixel electrode E1c, the gas may be fluently discharged through the openings OP1 and OP2, and the shrinkage caused by the outgassing may be suppressed.

A pixel defining layer 190 including openings 195a, 195b, and 195c overlapping the pixel electrodes E1a, E1b, and E1c may be positioned on the second insulating layer IL2. The opening 195c overlapping the third pixel electrode E1c may include portions 195c1 to 195c6 divided by the openings OP1 and OP2. The opening 195c is shown to be divided into the six portions 195c1 to 195c6, and the number of the divided portions may be changeable. The pixel defining layer 190 may cover edges of the pixel electrodes E1a, E1b, and E1c. The pixel defining layer 190 may cover the openings OP1 and OP2 of the third pixel electrode E1c. The pixel defining layer 190 may overlap the data lines DLa, DLb, and DLc.

A first emission layer ELa, a second emission layer ELb, and a third emission layer ELc may be positioned on the first pixel electrode E1a, the second pixel electrode E1b, and the third pixel electrode E1c. The first emission layer ELa, the second emission layer ELb, and the third emission layer ELc may be positioned in the respectively corresponding openings 195a, 195b, and 195c of the pixel defining layer 190. The first emission layer ELa, the second emission layer ELb, and the third emission layer ELc may have substantially the same planar shapes as the respectively corresponding openings 195a, 195b, and 195c, and the planar shapes may be substantially equivalent to the light emitting regions of the respective pixels PXa, PXb, and PXc. The third emission layer ELc may include portions ELc1 to ELc6 divided by the openings OP1 and OP2. The portions ELc1 to ELc6 of the third emission layer ELc may be positioned in the corresponding portions 195c1 to 195c6 of the opening 195c of the pixel defining layer 190. The portions ELc1 to ELc6 of the third emission layer ELc may have substantially same planar shapes as the corresponding portions 195c1 to 195c6 of the opening 195c of the pixel defining layer 190, and the planar shapes may be substantially equivalent to the light emitting region of the third pixel PXc. When the portions ELc1 to ELc6 of the third emission layer ELc are divided, they may be positioned on one third pixel electrode E1c for receiving the same driving current based on the same data voltage and may emit light with substantially the same brightness per area.

A common electrode E2 may be positioned on the pixel defining layer 190 and the emission layers ELa, ELb, and ELc. The common electrode E2 may be the cathode of the light emitting diode LED. The pixel electrodes E1a, E1b, and E1c, the emission layers ELa, ELb, and ELc, and the common electrode E2 may configure the light emitting diode LED in the respective pixels PXa, PXb, and PXc.

A capping layer (not shown) may be positioned on the common electrode E2, and an encapsulation layer (not shown) may be positioned on the capping layer.

FIG. 6 and FIG. 7 show top plan views of pixels disposed in a display area of a light emitting display device according to an embodiment.

Referring to FIG. 6, the shape of the first opening OP1 formed in the third pixel electrode E1c is different, compared to the above-described embodiment. In detail, the first opening OP1 may be formed to divide the third pixel electrode E1c into two portions E1c1 and E1c2. The first opening OP1 may extend in the second direction y and may divide the third pixel electrode E1c into a first portion E1c1 that is on a left side of the first opening OP1 and a second portion E1c2 that is on a right side of the first opening OP1. The first opening OP1 may extend in parallel to the third data line DLc and may overlap the third data line DLc. A width of the first opening OP1 may be greater than a width of the third data line DLc. When the first opening OP1 is formed as described above, the region where the third pixel electrode E1c overlaps the third data line DLc may be minimized and the parasitic capacitance C_AKbetween the third pixel electrode E1c and the third data line DLc may be further reduced. Although not shown, the first portion E1c1 and the second portion E1c2 of the third pixel electrode E1c may be electrically connected to each other and may receive the same driving current.

Referring to FIG. 7, there is a difference in that the second opening OP2 is not formed in the third pixel electrode E1c, compared to the above-described embodiment. Hence, the third emission layer ELc may include portions ELc1 and ELc2 divided by the first opening OP1. That is, the third emission layer ELc may include a first portion ELc1 positioned on the left side of the first opening OP1 and a second portion ELc2 positioned on the right side of the first opening OP1. When the third pixel electrode E1c and the third emission layer ELc are formed as described above, the light emitting region of the third pixel PXc may increase and a lifespan of the third pixel PXc may accordingly be increased. When the second opening OP2 is not formed in the third pixel electrode E1c, gas may be discharged through the first opening OP1, thereby improving the shrinkage caused by the outgassing. A plurality of first openings OP1 are spaced from each other, and they may be connected to each other and may be lengthily formed in the second direction y. As shown in FIG. 6, the first opening OP1 may be formed to divide the third pixel electrode E1c into two right and left portions.

FIG. 8 shows a top plan view of pixels disposed in a display area of a light emitting display device according to an embodiment.

Referring to FIG. 8, an example in which a first opening OP1 extending in the second direction y is formed in the pixel electrodes E1a and E1b of the first pixel PXa and the second pixel PXb from among the pixels PXa, PXb, and PXc. The first opening OP1 may extend to be parallel to the first data line DLa or the second data line DLb and overlap the same. The first emission layer ELa may be divided into two portions ELa1 and ELa2 by the first opening OP1. The second emission layer ELb may be divided by the first opening OP1, and it may not be divided and may substantially have a U shape. That is, the second emission layer ELb may include portions positioned on the right, left, and bottom (or top) side of the first opening OP1, and they may be connected to each other.

As described, formation of the first opening OP1 in the first pixel electrode E1a and the second pixel electrode E1b may be advantageous in the structure in which the first pixel PXa and the second pixel PXb are lengthily formed in the first direction x and the third pixel PXc is lengthily formed in the second direction y. By forming the first opening OP1 in the first pixel electrode E1a and the second pixel electrode E1b, the region in which the first pixel electrode E1a and the second pixel electrode E1b overlap the first data line DLa or the second data line DLb may be reduced. Therefore, the parasitic capacitance C_AKamong the first pixel electrode E1a and the second pixel electrode E1b and the first data line DLa or the second data line DLb may be reduced.

In addition, the third pixel electrode E1c may include a second opening OP2 extending in the first direction x, and the gas is discharged through the second opening OP2, thereby improving the shrinkage caused by the outgassing. The third emission layer ELc may be divided into two portions ELc1 and ELc2 or may not be divided.

The first pixel PXa, the second pixel PXb, and the third pixel PXc may be disposed to be evenly distributed. For example, the first pixel PXa and the second pixel PXb may be alternately and repeatedly disposed in the second direction y. The first and second pixels PXa and PXb and the third pixel PXc may be alternately and repeatedly disposed in the first direction x. Disposal of the pixels PXa, PXb, and PXc is modifiable in many ways.

FIG. 9 shows a cross-sectional view of a display panel according to an embodiment. Parts shown in FIG. 9 may correspond to substantially three pixel areas.

Referring to FIG. 9, the display panel 10 may include a display unit 100, a touch portion 200, and an antireflector 300.

The display unit 100 may include a substrate 110, transistors T3 and T6 formed on the substrate 110, a storage capacitor C_ST, and a light emitting diode LED. The light emitting diode LED may correspond to the pixel PX. FIG. 9 shows the third transistor T3 and the sixth transistor T6 from among the transistors T1 to T8 described with reference to FIG. 2, and the first, second, fifth, seventh, and eighth transistors T1, T2, T5, T7, and T8 may substantially have the same stacked structure as the sixth transistor T6, and the fourth transistor T4 may substantially have the same stacked structure as the third transistor T3.

The substrate 110 may be a flexible substrate including polymers such as a polyimide, a polyamide, or a polyethylene terephthalate. The substrate 110 may be a glass substrate.

A barrier layer 111 for preventing permeation of moisture or oxygen may be positioned on the substrate 110. The barrier layer 111 may include an inorganic insulating material such as a silicon nitride (SiN_x), a silicon nitride (SiO_x), or a silicon oxynitride (SiO_xN_y) and may be a single layer or a multilayer.

A buffer layer 120 may be positioned on the barrier layer 111. The buffer layer 120 may improve the characteristic of the semiconductor layer A6 by blocking impurities from the substrate 110 when the semiconductor layer A6 is formed, and may release the stress of the semiconductor layer A6 by planarizing the surface of the substrate 110. The buffer layer 120 may include an inorganic insulating material such as the silicon oxide, the silicon nitride, or the silicon oxynitride. The buffer layer 120 may include amorphous silicon.

The semiconductor layer A6 may be positioned on the buffer layer 120. The semiconductor layer A6 may include a first region, a second region, and a channel region between the two regions. The semiconductor layer A6 may include polysilicon.

A first gate insulating layer 141 may be positioned on the semiconductor layer A6. The first gate insulating layer 141 may include an inorganic insulating material such as the silicon nitride (SiN_x), the silicon oxide (SiO_x), or the silicon oxynitride (SiO_xN_y), and may be a single layer or a multilayer.

A first gate conductive layer including a gate electrode G6 and a first electrode C1 of the storage capacitor C_STmay be positioned on the first gate insulating layer 141. The first gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be a single layer or a multilayer.

A second gate insulating layer 142 may be positioned on the first gate conductive layer. The second gate insulating layer 142 may include an inorganic insulating material such as the silicon nitride, the silicon oxide, or the silicon oxynitride, and may be a single layer or a multilayer.

A second gate conductive layer including a light blocking layer LB and a second electrode C2 of the storage capacitor C_STmay be positioned on the second gate insulating layer 142. The second electrode C2, the first electrode C1, and the second gate insulating layer 142 between them may configure the storage capacitor C_ST. The light blocking layer LB may prevent the characteristic deterioration of the semiconductor layer A3 by blocking external light from reaching the semiconductor layer A3. The second gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be a single layer or a multilayer.

A first inter-layer insulating layer 161 may be positioned on the second gate conductive layer. The first inter-layer insulating layer 161 may include an inorganic insulating material such as the silicon nitride, the silicon oxide, or the silicon oxynitride, and may be a single layer or a multilayer. When the first inter-layer insulating layer 161 is a multilayer, the lower layer may include a silicon nitride and the upper layer may include a silicon oxide.

A semiconductor layer A3 may be positioned on the first inter-layer insulating layer 161. The semiconductor layer A3 may overlap the light blocking layer LB. The semiconductor layer A3 may include a first region, a second region, and a channel region between the two regions. The semiconductor layer A3 may include an oxide semiconductor. The semiconductor layer A3 may include at least one of zinc (Zn), indium (In), gallium (Ga), and tin (Sn). For example, the semiconductor layer A3 may include an indium-gallium-zinc oxide (IGZO).

A third gate insulating layer 143 may be positioned on the semiconductor layer A3. The third gate insulating layer 143 may include an inorganic insulating material such as the silicon nitride, the silicon oxide, or the silicon oxynitride, and may be a single layer or a multilayer.

A third gate conductive layer including a gate electrode G3 may be positioned on the third gate insulating layer 143. The third gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may be a single layer or a multilayer. For example, the third gate conductive layer may include a lower layer including titanium and an upper layer including molybdenum, and the lower layer may prevent fluorine (F) that is an etching gas from being spread when the upper layer is dry etched.

A second inter-layer insulating layer 162 may be positioned on the third gate conductive layer. The second inter-layer insulating layer 162 may include an inorganic insulating material such as the silicon nitride, the silicon oxide, or the silicon oxynitride, and may be a single layer or a multilayer. The second inter-layer insulating layer 162 may, for example, include a lower layer including a silicon nitride and an upper layer including a silicon oxide.

A first data conductive layer including first electrodes S3 and S6, second electrodes D3 and D6, and a gate line GL may be positioned on the second inter-layer insulating layer 162. The first electrode S3 and the second electrode D3 may be respectively connected to the first region and the second region of the semiconductor layer A3 through contact holes formed in the insulating layers 143 and 162. The first electrode S6 and the second electrode D6 may be respectively connected to the first region and the second region of the semiconductor layer A6 through contact holes formed in the insulating layers 141 142, 161, 143, and 162. The gate line GL may be a scan line GL1, an inverted scan line GL2, an initialization control line GL3, a bypass control line GL4, or a light emitting control line GL5. The first data conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be a single layer or a multilayer. For example, the first data conductive layer may include a lower layer including a refractory metal such as molybdenum, chromium, tantalum, or titanium, an intermediate layer including a metal with low resistivity such as aluminum, copper, or silver, and an upper layer including a refractory metal. For example, the first data conductive layer may have a triple-layered structure such as titanium (Ti)-aluminum (Al)-titanium (Ti).