. The outer signal line layer 160 is arranged on a surface of the second side of the insulating dielectric material 100, and is connected with the inner signal line layer 150 through a TMV structure. The inner signal line layer 150 includes a first inner signal line layer and a second inner signal line layer 153. A plurality of the first inner signal line layers are provided, and the plurality of the first inner signal line layers include a first line layer, a second line layer, . . . , and an M^thline layer, where M is an integer greater than 1. The second inner signal line layer, the first line layer, the second line layer, . . . , and the M^thline layer are sequentially laminated from the first side to the second side of the insulating dielectric material 100. The first inner signal line layers are provided with two layers in this embodiment, that is, the plurality of the first inner signal line layers include a first line layer 151 and a second line layer 152. The second inner signal line layer 153 and the first line layer 151 are connected through a first metal column 131, the first line layer 151 and the second line layer 152 are connected through a second metal column 133, and so on. Conductive structures such as the first metal column 131 and the second metal column 133 may be used as the second conductive metal column for electrically-conductive connection between different line layers, that is, the adjacent inner signal line layers 150 are connected through the second conductive metal column. In this embodiment, a conventional Via hole or a first conductive metal column may be employed as the TMV structure. In the conventional TMV structure, the Via hole is formed by laser and electroplating, which can carry out signal transmission in the packaging layer 120, thus realizing signal transmission between the outer signal line layer 160 and the inner signal line layer 150. However, upper and lower apertures of the Via hole are quite different, which is difficult to form a solid conductive structure, and a wall of the hole is rough. In order to improve the conductivity of the TMV structure, a metal column structure, which is the first conductive metal column 140, is employed as the TMV structure. The first conductive metal column 140 and the second conductive metal column in this embodiment are both solid copper columns, which can achieve almost the same upper and lower apertures and have smooth surfaces. Compared with the conventional Via hole, the solid copper column has a smaller signal loss, shorter signal transmission delay and better conductivity. The first conductive metal column 140 of this embodiment may be obtained by a copper column method or a metal column mounting method. Referring to FIG. 1, when the first conductive metal column 140 is obtained by the copper column method, the first conductive metal column 140 is directly connected with the inner signal line layer 150. Referring to FIG. 2, when the first conductive metal column 140 is obtained by the metal column mounting method, a tin solder 141 is connected between the first conductive metal column 140 and the inner signal line layer 150. To avoid repetition, please refer to the example embodiment five for the specific machining method of the first conductive metal column 140.

The heat dissipation metal face 170 is arranged on a surface of the first side of the insulating dielectric material 100, where the heat dissipation metal face 170 and the inner signal line layer 150 are separated through the isolating layer. The chip 180 is provided with an active face and a passive face which are opposite to each other, the chip 180 is embedded in the insulating dielectric material 100, the active face of the chip 180 is in electrically-conductive connection with the inner signal line layer 150, and the passive face of the chip 180 is in heat transfer connection with the heat dissipation metal face 170. When in use, the outer signal line layer 160 is configured for soldering with a PCB, so that wiring areas of the surfaces of the first side and the second side of the insulating dielectric material 100 can be fully utilized, which is beneficial for increasing an area of the heat dissipation metal face 170. It is conceivable that the active face of the chip 180 is provided with signal pins, and the signal pins of the chip 180 are electrically connected with the inner signal line layer 150 by wire-bonding. A thermally-conductive metal is connected between the passive surface of the chip 180 and the heat dissipation metal face 170, and the heat generated by the chip 180 in the working process is transferred to the heat dissipation metal face 170 through the thermally-conductive metal. The heat dissipation metal face 170 is a copper skin covering the surface of the first side of the insulating dielectric material 100, which has a larger heat-dissipating area and can improve the heat dissipation efficiency of the chip 180. Furthermore, the heat dissipation metal face 170 and the inner signal line layer 150 are isolated by the isolating layer, which can separate the signal layer from the heat dissipation layer, thereby realizing heat and signal separation, avoiding the limited heat dissipation area caused by the co-layer of the signal layer and the heat dissipation layer, and greatly improving the heat dissipation effect. In this embodiment, the thermally-conductive metal includes a thermally-conductive metal face 532 and a thermally-conductive metal column 533. A first side of the thermally-conductive metal face 532 is connected with the passive surface of the chip 180, and a second side of the thermally-conductive metal face 532 is connected with the heat dissipation metal face 170 through the thermally-conductive metal column 533. The thermally-conductive metal face 532 may adapt to the chips 180 with different areas and transfer the heat generated by the chips 180. The thermally-conductive metal column 533 may transfer the heat of the thermally-conductive metal face 532 to the heat dissipation metal face 170, and a thickness of the thermally-conductive metal column 533 may be adjusted according to thicknesses of different isolating layers, which can address the problem of the thickness limitation of the thermally-conductive metal face 532.

Example Embodiment Two

Referring to FIG. 3, this embodiment discloses a signal-heat separated TMV packaging structure, including an insulating dielectric material 100, an inner signal line layer 150, an outer signal line layer 160, a heat dissipation metal face 170 and a chip 180.

FIG. 3 illustrates a schematic cross-sectional structure of the insulating dielectric material 100 in a thickness direction thereof. The insulating dielectric material 100 has a first side and a second side which are opposite to each other, the insulating dielectric material 100 includes a plurality of insulating layers, and the insulating layers are coated or laminated with a first insulating dielectric material. The plurality of insulating layers includes a first insulating layer, a second insulating layer, . . . , and an L^thinsulating layer, and L is an integer greater than or equal to 1. The first insulating layer, the second insulating layer, . . . , and the L^thinsulating layer are sequentially laminated from the first side to the second side of the insulating dielectric material 100. Two insulating layers are provided in this embodiment, that is, the plurality of insulating layers include a first insulating layer 111 and a second insulating layer 112, where the first insulating layer 111 is arranged at the first side of the insulating dielectric material 100 and served as the isolating layer. The plurality of insulating layers define a packaging cavity 101. The packaging cavity 101 is configured for accommodating the chip 180, and the insulating dielectric material 100 further includes a packaging layer 120. The packaging layer 120 covers the adjacent insulating layer, that is, the L^thinsulating layer, is filled in the packaging cavity 101, and wraps around the chip 180. The packaging layer 120 is obtained by packaging with the second insulating dielectric material, and the packaging layer 120 is configured for packaging the chip 180 in the packaging cavity 101. In this way, the chip 180 can be embedded in the insulating dielectric material 100, which is beneficial to realize higher-density integrated packaging.

The inner signal line layer 150 is arranged in the insulating dielectric material 100. The outer signal line layer 160 is arranged on a surface of the second side of the insulating dielectric material 100, and is connected with the inner signal line layer 150 through a TMV structure. The inner signal line layer 150 in this embodiment includes a plurality of first inner signal line layers, and the plurality of the first inner signal line layers include a first line layer, a second line layer, . . . , and an M^thline layer, where M is an integer greater than or equal to 1. The first line layer, the second line layer, . . . , and the M^thline layer are sequentially laminated from the first side to the second side of the insulating dielectric material 100. The first inner signal line layers are provided two layers in this embodiment, that is, the plurality of the first inner signal line layers include a first line layer 151 and a second line layer 152. The first line layer 151 and the second line layer 152 are connected through a second metal column 133, the second line layer 152 and the third line layer (not shown in the figure) are connected through a third metal column (not shown in the figure), and so on. Conductive structures such as the second metal column 133 and the third metal column may be used as the second conductive metal column for electrically-conductive connection between different line layers, that is, the adjacent inner signal line layers 150 are connected through the second conductive metal column. It should be noted that the TMV structure of this embodiment is the same as that of the example embodiment one, and will not be elaborated in this embodiment. The first conductive metal column 140 and the second conductive metal column in this embodiment are both solid copper columns, which can achieve almost the same upper and lower apertures and have smooth surfaces. Compared with the conventional Via hole, the solid copper column has a smaller signal loss, shorter signal transmission delay and better conductivity. The first conductive metal column 140 of this embodiment may be obtained by a copper column method or a metal column mounting method. Referring to FIG. 3, when the first conductive metal column 140 is obtained by the copper column method, the first conductive metal column 140 is directly connected with the inner signal line layer 150. Referring to FIG. 4, when the first conductive metal column 140 is obtained by the metal column mounting method, a tin solder 141 is connected between the first conductive metal column 140 and the inner signal line layer 150. To avoid repetition, please refer to the example embodiment five for the specific machining method of the first conductive metal column 140.

The heat dissipation metal face 170 is arranged on a surface of the first side of the insulating dielectric material 100, where the heat dissipation metal face 170 and the inner signal line layer 150 are separated through the isolating layer. The chip 180 is provided with an active face and a passive face which are opposite to each other, the chip 180 is embedded in the insulating dielectric material 100, the active face of the chip 180 is in electrically-conductive connection with the inner signal line layer 150, and the passive face of the chip 180 is in heat transfer connection with the heat dissipation metal face 170. When in use, the outer signal line layer 160 is configured for soldering with a PCB, so that wiring areas of the surfaces of the first side and the second side of the insulating dielectric material 100 can be fully utilized, which is beneficial for increasing an area of the heat dissipation metal face 170. It is conceivable that the active face of the chip 180 is provided with signal pins, and the signal pins of the chip 180 are electrically connected with the inner signal line layer 150 by wire-bonding. The passive surface of the chip 180 is directly contacted with the heat dissipation metal face 170, and the heat generated by the chip 180 in the working process is transferred to the heat dissipation metal face 170 through the thermally-conductive metal. The heat dissipation metal face 170 is a copper skin covering the surface of the first side of the insulating dielectric material 100, which has a larger heat-dissipating area and can improve the heat dissipation efficiency of the chip 180. Furthermore, the heat dissipation metal face 170 and the inner signal line layer 150 are isolated by the isolating layer, which can separate the signal layer from the heat dissipation layer, thereby realizing heat and signal separation, avoiding the limited heat dissipation area caused by the co-layer of the signal layer and the heat dissipation layer, and greatly improving the heat dissipation effect. It should be noted that the contents not involved in this embodiment may refer to the example embodiment one.

Example Embodiment Three

This embodiment discloses a signal-heat separated TMV packaging structure (not shown in the figure), including an insulating dielectric material 100, an inner signal line layer 150, an outer signal line layer 160, a heat dissipation metal face 170 and a chip 180. Different from the example embodiment two, the insulating dielectric material 100 of this embodiment includes an insulating layer and a packaging layer 120. The insulating layer is a single-layer or multi-layer structure, and the inner signal line layer 150 is a single-layer structure (not shown in the figure). The inner signal line layer 150 is arranged on the insulating layer and located at a junction with the packaging layer.

Example Embodiment Four

This embodiment provides a manufacturing method of a substrate, including steps S010 to S090. Each step will be described in detail below.

At S10, referring to FIG. 5, a bearing plate 010 is provided, where the bearing plate 010 includes a core layer 011, a first metal layer 012, a second metal layer 013, an etching barrier layer 014 and a first metal seed layer 015, where the first metal layer 012 and the second metal layer 013 may be copper layers, which may be physically combined and can be separated. After the first metal layer 012 and the second metal layer 013 are separated, an etching process is needed. The etching barrier layer 014 can protect lines of the substrate and metal columns from over-etching. The etching barrier layer 014 may be a nickel layer, and the first metal seed layer 015 may be a copper layer, which is used as a conduction basis for subsequent electroplating.

At S020, referring to FIG. 6, a first photoresist 021 is applied on the bearing plate 010, and a first metal column layer is obtained by opening windows through the first photoresist 021 and conducting electroplating. The first metal column layer of this embodiment is obtained by a copper column method, where the first photoresist 021 may be obtained by pasting or coating, and the method of opening windows in the first photoresist 021 may include processes of exposure and development. According to different actual application requirements, the first metal column layer may include a first metal column 131 and a first sacrificial metal column 132, or the first metal column layer includes the first sacrificial metal column 132, with the first metal column 131 omitted. FIG. 7 illustrates a top view structure of the windows in the first photoresist 021. It should be understood that the first metal column layer of this embodiment is a copper column layer, and shapes of the windows 211 in the first photoresist 021 are adapted respectively with the first metal column 131 and the first sacrificial metal column 132.

At S030, referring to FIG. 7, FIG. 8 and FIG. 9, the first photoresist 021 is removed and a first insulating dielectric material is applied to form a first insulating layer 111. The first insulating dielectric material may be pure resin or an organic insulating material containing resin and glass fiber, and the first insulating dielectric material may be applied on the first metal column layer by coating or pressing to form the first insulating layer 111.

At S040, referring to FIG. 9, FIG. 10 and FIG. 11, after thinning the first insulating layer 111, a second photoresist 022 is applied on the first insulating layer 111, and a first line layer 151 is obtained by opening windows in the second photoresist 022 and conducting electroplating. Corresponding to step S020, the first line layer 151 may include a first conductive line 511 and a first sacrificial line 512, the first sacrificial line 512 is connected with the first sacrificial metal column 132, or the first line layer 151 may includes the first sacrificial line 512, with the first conductive line 511 omitted. It should be noted that when the first metal column 131 is provided, the first conductive line 511 may be connected with the first metal column 131.

At S050, referring to FIG. 12 and FIG. 13, a third photoresist 023 is applied on the first line layer 151, and a second metal column layer is obtained by opening windows in the third photoresist 023 and conducting electroplating. Corresponding to the first metal column layer, the second metal column layer includes a second metal column 133 and a second sacrificial metal column 134, or the second metal column layer includes the second sacrificial metal column 134, with the second metal column 133 omitted.

At S060, referring to FIG. 13 and FIG. 14, the third photoresist 023 is removed and a first insulating dielectric material is applied to form a second insulating layer 112.

At S070, the steps S030 to S060 are repeated until the number of layers of the substrate meets the requirements of production means. It should be noted that the sacrificial lines serve to facilitate the machining and alignment of the next layer of sacrificial metal column. Therefore, the sacrificial lines may be omitted on the last line layer. For example, referring to FIG. 15, when the second line layer 152 is the last line layer, the second line layer 152 includes the second conductive line, with the second sacrificial line omitted.

At S080, referring to FIG. 15, FIG. 16 and FIG. 17, after the bearing plate 010 is separated, the sacrificial line and the sacrificial metal column are etched to form a packaging cavity 101. It should be noted that a fourth photoresist 024 may be applied in the etching process to protect parts that do not need etching.

At S090, after removing the fourth photoresist 024, the substrate is obtained. It should be noted that the first metal column 131 may be arranged on the substrate (as shown in FIG. 18), or the first metal column 131 may be omitted (as shown in FIG. 19) according to different actual application requirements.

Example Embodiment Five

This embodiment provides a manufacturing method of a signal-heat separated TMV packaging structure, including steps S110 to S160. Each step will be described in detail below.

At S110, referring to FIG. 20, a substrate is provided, where the substrate has a first side and a second side which are opposite to each other, and a temporary bearing surface 030 is machined on a surface of the second side of the substrate.

The manufacturing method of the substrate may refer to the example embodiment four. It may be known from the manufacturing method of the example embodiment four that the substrate includes a first insulating layer, a second insulating layer, . . . , and an (N−1)^thinsulating layer, where N is an integer greater than 1. In this embodiment, the substrate is provided with a packaging cavity 101, a first inner signal line layer and a first metal column 131. The packaging cavity 101 extends across the first side and the second side of the substrate which are opposite to each other, the first inner signal line layer is partially or completely arranged on a surface of the first side of the substrate, a first end of the first metal column 131 is in electrically-conductive connection with the first inner signal line layer, a second end of the first metal column 131 is exposed to the surface of the second side of the substrate, and the temporary bearing surface 030 covers the packaging cavity 101. It should be noted that the first inner signal line layer includes a first line layer, a second line layer, . . . , and an M^thline layer, where M is an integer greater than or equal to 1. The first line layer is connected with the first metal column 131, and the second line layer is connected with the first line layer through a second metal column 133. By analogy, the M^thline layer and the (M−1)^thline layer are connected by an M^thmetal column, and the conductive structures such as the first metal column 131, the second metal column 133, . . . , and the M^thmetal column may be used as the second conductive metal columns for electrically-conductive connection between different line layers, that is, the first inner signal line layer includes a plurality of line layers, where one of the line layers is arranged on a surface of the first side of the substrate, the other line layers are embedded in the substrate, and the plurality of line layers are connected by metal columns. Alternatively, the first inner signal line layer includes a single line layer, and the single line layer is arranged on the surface of the first side of the substrate. For convenience of description, the first inner signal line layer of this embodiment includes a first line layer 151 and a second line layer 152.

In this embodiment, the machining method of the temporary bearing surface 030 may be obtained by sticking adhesive tape or adhesive plaster, and the temporary bearing surface 030 may provide support for mounting the chip 180, and expose the passive surface of the chip 180 after the subsequent packaging.

At S120, the chip 180 to be packaged is mounted in the packaging cavity 101 and wire-bonded with the second inner signal line layer, where an active face of the chip 180 faces the first side of the substrate, and the passive surface of the chip 180 is connected with the temporary bearing surface 030. It should be noted that the first inner signal line layer wire-bonded with the chip 180 is the outermost line layer of the substrate, that is, the M^thline layer.

At S130, referring to FIG. 20, FIG. 21 and FIG. 22, a first conductive metal column 140 is machined on the first side of the substrate, and the chip is packaged by a second insulating dielectric material to form a packaging layer 120, where the first conductive metal column 140 is connected with the first inner signal line layer.

The first conductive metal column 140 is used as a signal transmission structure between the first inner signal line layer and the outer signal line layer 160. The first conductive metal column 140 may be obtained by a metal column mounting method or a copper column method, which can make both ends of the first conductive metal column 140 have almost the same aperture and have smooth surfaces. Compared with the conventional Via hole, the solid copper column has a smaller signal loss, shorter signal transmission delay and better conductivity. Packaging the chip by the second insulating dielectric material can protect the chip 180 and provide a bearing for manufacturing the subsequent outer signal line layer 160.

At S140, referring to FIG. 22 and FIG. 23, the temporary bearing surface 030 is removed, and a second inner signal line layer 153 is machined on a surface of the second side of the substrate. The second inner signal line layer 153 includes a second inner signal line 531 and a thermally-conductive metal face 532, the second inner signal line 531 is connected with the first metal column 131, and the thermally-conductive metal face 532 is connected with the passive face of the chip 180.

Machining the second inner signal line layer 153 on the surface of the second side of the substrate can meet the requirements on line layers of different packaging designs, and can make full use of the longitudinal space of the packaging body to realize high-density integration. The thermally-conductive metal face 532 is used for transferring heat generated by the chip 180.

At S150, referring to FIG. 23 and FIG. 24, a thermally-conductive metal column 533 is machined on the thermally-conductive metal face 532 and laminated to form an isolating layer.

The thermally-conductive metal column 533 may be obtained by a copper column method, that is, by the steps of applying photoresist, and opening windows in the photoresist and conducting electroplating. After machining the thermally-conductive metal column 533, the first insulating dielectric material is laminated and pressed on the thermally-conductive metal column 533, and the first insulating dielectric material is formed into an N^thinsulating layer, which may be used as an isolating layer for separating the signal layer from the heat dissipation layer.

At S160, referring to FIG. 24 and FIG. 25, an outer signal line layer 160 is machined on a surface of the packaging layer 120 and a heat dissipation metal face 170 is machined on a surface of the isolating layer, where the outer signal line layer 160 is connected with the first conductive metal column 140, and the heat dissipation metal face 170 is connected with the thermally-conductive metal column 533.

It should be noted that in step S130, the second insulating dielectric material is higher than the first conductive metal column 140, so the packaging layer 120 needs to be thinned before machining the outer signal line layer 160. When in use, the outer signal line 160 may be welded with a PCB, and the heat dissipation metal face 170 covers a surface of the isolating layer, which has a large heat dissipation area, and is conducive to improving the heat dissipation efficiency. Moreover, the heat dissipation metal face 170 is separated from the inner signal line and the outer signal line 160, thus realizing signal and heat separation, avoiding limited heat dissipation area caused by the co-layer of the signal layer and the heat dissipation layer, and greatly improving the heat dissipation effect.

Therefore, in this embodiment, the chip 180 is mounted in the packaging cavity 101, which is beneficial to realize higher-density integrated packaging. The heat dissipation metal face 170 and the second inner signal line layer are separated by the isolating layer, which can realize signal and heat separation, and greatly improve the heat dissipation effect.

This embodiment provides two machining methods of the first conductive metal column 140, where the first machining method is as follows.

Referring to FIG. 25, “machining the first conductive metal column 140 on the first side of the substrate” in step S130 includes:

S131a: mounting the first conductive metal column 140 on the first side of the substrate at a position corresponding to the first inner signal line layer; and S131b: welding the first conductive metal column 140 with the second inner signal line layer through a tin solder 141.

By machining the first conductive metal column 140 in a mounting way, the first metal column 131 can have a regular shape and a smooth surface, which is conducive to improving the conductivity.

The second machining method is as follows.

Referring to