At this stage, the corners of the coupon may become exposed (as shown in FIG. 15) and the top of the tethers may be exposed to release etchant. However, the provision of an additional photoresist protection layer as per the present disclosure ensures that even if the corners are exposed the tethers will not be exposed to the release etchant. Therefore a ledge-less process can be provided where leakage is not of concern.

The coupon, tethers, and support pillars are then covered with resist 1602 as shown in FIGS. 16A (perspective) and 16B (top-down view). The coupon is now ready for release and use in a micro-transfer printing process. After release, the coupon can be cleaned with isopropyl alcohol (IPA) or acetone before deionized water (DI) to remove the resist. FIGS. 17A and 17B show an alternative to FIGS. 16A and 16B, where the resist 1702 is only applied to cover the facet and supports. FIG. 18 is a perspective figure showing the undercuts after release. As can be seen, the undercut 1804 under the coupon and tethers is a full undercut and so the device coupon and tethers do not directly contact the wafer. In contrast, the undercut 1802 on the remaining wafer is only a partial undercut so that the release layer 610 is still present.

FIGS. 19A and 19B show, respectively, cross-sectional and top-down views of a variant device wafer. The device wafer includes a reflective semiconductor optical amplifier (RSOA) or another photonic device or device coupon 1900 denoted by the dashed region. As will be discussed in detail below, the device includes various semiconductor layers, electrical contacts, and other features. Of note is first etch stop layer 1902 which, as discussed in detail below, is used to improve the manufacturability of the device. The device 1900 also includes an active or gain region 1904 which is a layer of semiconductor. The facet 1906 of the device is coated in an antireflective coating. There is a second etch stop layer 1908 which, as also discussed in detail below, improves the manufacturability of the device. There is also a semiconductor tether layer 1910 which provides to tethers 1912 which connect the device 1900 to anchors 1914 formed in trenches 1916. In FIGS. 19A and 19B the release layer has not yet been removed, and so can be seen underneath the device. FIG. 19B shows the same device wafer as FIG. 19A but from a top-down perspective. The plurality of tethers 1914 (two labelled for clarity) can be seen around the periphery of the device 1900. The release layer 1930 can also be seen, as well as the trenches 1916 extending around the outer periphery of the coupon.

FIGS. 20(i) to 20(xxvi) show various steps of a method of preparing the device coupon of FIGS. 19A and 19B. In FIG. 20(i), an initial epitaxial wafer is provided. The initial epitaxial wafer includes, for example and in bottommost to uppermost layer, a substrate 1932, release layer 1930, tether layer 1910, second etch stop layer 1908, first intermediate semiconductor layer 1934, active or gain layer 1904, second intermediate semiconductor layer 1936, first etch stop layer 1902, and upper semiconductor layer 1938. The layers may have thicknesses as follows: substrate 1932—350,000 nm; release layer 1930—500 nm; tether layer 1910—500 nm; second etch stop layer 1908—20 nm; first intermediate semiconductor layer 1934—1500 nm; active or gain layer 1604—400 nm; second intermediate semiconductor layer 1936—1500 nm; first etch stop layer 1902—20 nm; and upper semiconductor layer 1938—1900 nm. Next, as shown in FIG. 20(ii), a hard mask 2000 is patterned onto the epitaxial wafer and a ridge 2002 is etched (via either a dry or wet etch) to the first etch stop. The hard mask is then stripped off, as shown in FIG. 20(iii). A new hard mask 2004 is then deposited over the wafer. The result of this is shown in FIG. 20(iv). The hard mask 2004 is then patterned and an etch, in this example a dry etch, is performed so as to expose a surface of the first intermediate semiconductor layer 1934 (also referred to as the n-doped layer) as shown in FIG. 20(v). This etch provides a via 2006 which is subsequently used to make the n-contact.

Next, as shown in FIG. 20(vi), the hard mask 2004 is then stripped and then a further hard mask 2008 is deposited as shown in FIG. 20(vii). This further hard mask is patterned and an etch (either wet or dry) is performed down to the second etch stop 1908. This etch defines the height of the resulting tether layer 1910. The result is shown in FIG. 20(viii). A self-aligned etch is then performed, which defines the facet of the device coupon and also the tethers surrounding the device (as shown in FIG. 19B), with the structure shown in FIG. 20(ix) resulting. The use of the second etch-stop in this step allows the tethers to be formed of semiconductor with a thickness accuracy limited only by variations during epitaxial growth (typically less than 10%). Next, in a step shown in FIG. 20(x), the trenches 1916 are etched into the wafer which provides the anchors discussed previously. The hard mask 2008 is then stripped as also shown in FIG. 20(x). A dielectric layer 2010, for example formed of silicon dioxide, is then deposited over the wafer as shown in FIG. 20(xi). This dielectric layer also lines the trenches, which ensures that the release layer etchant is contained and the mechanically weak points are always the semiconductor tethers. An n-contact opening 2012 is then formed in a part of the dielectric layer 2010 within the via for the n-contact, thereby exposing an upper surface of the first intermediate semiconductor layer 1934. This is shown in FIG. 20(xii). The n-contact 2014 is then deposited as shown in FIG. 20(xiii). Next, as shown in FIG. 20(xiv), a portion of the dielectric 2010 is etched away to provide a p-contact opening 2016 and expose an upper surface of the upper semiconductor layer 1938. The p-contact 2018 is then deposited as shown in FIG. 20(xv).

Next, routing metal 2020 is deposited and etched as shown in FIG. 20(xvi). After this, in a step shown in FIG. 20(xvii), the dielectric is etched to clear the facets and tethers. An antireflective coating