and the second transistor 208 are P-channel MOSFETs (pMOSFETs). Alternatively, the first transistor 206 and/or the second transistor 208 may be P-channel field-effect transistors (FETs), P-channel insulated-gate bipolar transistors (IGBTs), P-channel junction field effect transistors (JFETs), or PNP bipolar junction transistor (BJTs). The first transistor 206 and the second transistor 208 may be of equal size (e.g., gate width and/or length, channel width and/or length, etc.) and are to receive equal or approximately equal signals.

In FIG. 2, the max selector logic 204 includes an example third transistor 210 and an example fourth transistor 212. The third transistor 210 includes a drain, a source, a gate, and a bulk terminal. The drain of the third transistor 210 is coupled to the source of the fourth transistor 212. The source of the third transistor 210 is coupled to a second current source 216. The gate of the third transistor 210 is configured to receive the first input signal (INP) and the gate of the fourth transistor 212 is configured to receive the second input signal (INN). The bulk terminals of the third transistor 210 and the fourth transistor 212 are tied to (e.g., coupled to) the source of the third transistor 210 at the bias node (B) and to the bulk terminals of the first and second transistors 206, 208 at a bias node (B).

In some examples, an unregulated condition may occur at the main input pair 202 and there is a differential voltage between the first and second transistors 206, 208. In such an example (e.g., where the bulk terminals are not connected as shown in FIG. 2), the bulk voltage at the bulk terminal of the first transistor 206 may be less than the gate voltage at the gate of the first transistor 206 and/or less than the source voltage (e.g., the supply voltage) at the source of the first transistor 206. For example, the first transistor 206 may receive a gate voltage of five volts and the second transistor 208 receives a gate voltage of zero volts. In such an example, the bulk voltage is lower than the gate voltage. When the bulk voltage is lower than the gate voltage, PBTI may occur (e.g., under certain circumstances, such as during periods of higher ambient temperatures) and causes the degradation of precision and/or performance of the complimentary transistors.

In this example, to avoid the PBTI effect, the bulk terminals of the first and second transistors 206, 208 are biased to the voltage at bias node B. The voltage at the bias node B is determined based on which input voltage (INP, INN) is higher. For example, if INP is five volts greater than INN, the third transistor 210 may be off and/or conducting minimum current relative to the fourth transistor 212 responsive to the higher INP input voltage. Therefore, the voltage at the bias node B may be the gate to source voltage (V_GS) plus the voltage of INP. For example, the potential of the bulk terminal of the third transistor 210 follows the potential of the gate of the third transistor 210. The bulk terminal of the third transistor 210 is coupled to the bias node B and determines the potential at the bias node B responsive to INP having a greater voltage than INN. In this manner, the bulk terminals of the first transistor 206 and the second transistor 208 are biased to a greater voltage than the highest input voltage. As such, stress from PBTI due to positive gate-to-bulk voltage does not occur. In some examples, the voltage at node B stabilizes at approximately the value of the supply voltage, if the bulk voltage is approximately equal to the supply voltage.

In some examples, INN is greater than INP. For example, INN may be five volts greater than INP. The third transistor 210, in this example, enters into linear mode (e.g., conducts current linearly as INP decreases and/or increases) responsive to the lower voltage on INP. The fourth transistor 212 turns off (e.g., does not conduct current) and/or conducts minimum current relative to the third transistor 210. The voltage at the bias node B is one threshold voltage greater than the voltage of INN responsive to the high input voltage (INN) at the gate of the fourth transistor 212. For example, the potential of the bulk terminal of the fourth transistor 212 follows the potential at the gate of the fourth transistor 212 because the bulk terminal is shorted to the source terminal, and the voltage potential at the source terminal follows the gate voltage. The bulk terminal of the fourth transistor 212 is coupled to the bias node B and determines the potential at bias node B responsive to INN having a greater voltage than INP. For example, the the gate-to-source voltage (e.g., the threshold voltage plus overdrive, where overdrive is an additional voltage used to set the desired current through the transistor) of the fourth transistor 212 sets the potential at bias node B. In this manner, the bulk terminals of the first transistor 206 and the second transistor 208 are biased to a greater voltage than the highest input voltage (e.g., greater than the voltage of INN). As such, no PBTI occurs.

FIG. 3 is a schematic diagram of an example second input circuitry 300 to facilitate protecting an example main input pair 302 from degradation during an unregulated condition. In this example, the second input circuitry 300 reduces and/or eliminates the negative effects of NBTI on the main input pair 302. The example second input circuitry 300 includes the example main input pair 302, an example auxiliary input pair 304, an example window comparator 306, an example logic gate 308, example source follower circuitry 310, and example current steering circuitry 312.

In FIG. 3, the main input pair 302 includes an example first transistor 314 and an example second transistor 316. In some examples, the main input pair 302 may be implemented by the input circuitry 102 of FIG. 1 and/or the main input pair 202 of FIG. 2. The first transistor 314 includes a drain, a source, and a gate. The second transistor 316 includes a drain, a source, and a gate. The gate of the first transistor 314 is configured to receive the first input signal (INP) and the gate of the second transistor 316 is configured to receive the second input signal (INN). The source of the first transistor 314 is coupled to the source of the second transistor 316. The first transistor 314 and the second transistor 316 are P-channel MOSFETs (pMOSFETs). Alternatively, the first transistor 314 and the second transistor 316 may be P-channel field-effect transistors (FETs), P-channel insulated-gate bipolar transistors (IGBTs), P-channel junction field effect transistors (JFETs), or PNP bipolar junction transistor (BJTs). The first transistor 314 and the second transistor 316 are of equal size and are configured to obtain equal and/or approximately equal signals.

In FIG. 3, the auxiliary input pair 304 includes a third transistor 318 and a fourth transistor 320. The third transistor 318 includes a drain, a source. The fourth transistor 320 includes a drain, a source, and a gate. The gate of the third transistor 318 is configured to receive the first input signal (INP) and the gate of the fourth transistor 320 is configured to receive the second input signal (INN). The source of the third transistor 318 is coupled to the source of the fourth transistor 320. The third transistor 318 and the fourth transistor 320 are P-channel MOSFETs (pMOSFETs). Alternatively, the third transistor 318 and the fourth transistor 320 may be P-channel field-effect transistors (FETs), P-channel insulated-gate bipolar transistors (IGBTs), P-channel junction field effect transistors (JFETs), or PNP bipolar junction transistor (BJTs).

In FIG. 3, the second input circuitry 300 includes the window comparator 306 to compare the differential voltage between the first input (INP) and the second input (INN) to a an input differential threshold voltage. The input differential threshold voltage is indicative of an unregulated condition of the second input circuitry 300. For example, the input differential threshold voltage may be derived by determining the lowest amount of difference between the two inputs that would cause degradation of the main input pair 302. For example, the input differential threshold voltage may be an amount of voltage difference between INP and INN that begins to cause degradation of the first and second transistors 314, 316. In some examples, the input differential threshold voltage is derived by determining a differential voltage that ensures degradation of the first transistor 314 and/or the second transistor 316 (e.g., aging degradation of transistors 314, 316 due to NBTI and/or PBTI) is less than the threshold voltage of the comparator 306 to prevent the comparator 306 from outputting incorrect decisions (e.g., triggering at undesired and/or incorrect times). The window comparator 306 may be used to control the operation of the main input pair 302 and the auxiliary input pair 304. The non-inverting input of window comparator 306 is configured to receive the first input INP and the inverting input is configured to receive the second input INN. The window comparator 306 includes an output.

In FIG. 3, the logic gate 308 is implemented by an inverter. Additionally and/or alternatively, the logic gate 308 may be implemented by a logic AND gate, a logic OR gate, and/or any type of logic gate. In some examples, the logic gate 308 may be implemented by any combination of discrete transistors and/or other circuits elements that effect the function described herein based on analog signals. The logic gate 308 is coupled to the output of the window comparator 306. The logic gate 308 may be used to generate a signal that is complimentary to the signal generated by the window comparator 306.

In FIG. 3, the source follower circuitry 310 includes a fifth transistor 322, a sixth transistor 324, and a first current source 330. The fifth transistor 322 includes a drain, a source, and a gate. The sixth transistor 324 includes a drain, a source, and a gate. The source of the fifth transistor 322 is coupled to the drain of the sixth transistor 324. The gate of the fifth transistor 322 is configured to receive the value of the input (such as the first input (INP) and the second input (INN)) potential. For example, the gate of the fifth transistor 322 is configured to receive the lowest voltage magnitude between the first input (INP) and the second input (INN). In this example, the lowest input is selected by implementing logic circuitry. In some examples, the lowest input is selected by implementing analog circuitry.

The gate of the sixth transistor 324 is coupled to the output of the window comparator 306. The source of the sixth transistor 324 is coupled to the first current source 330 (which is coupled to ground). The sources of the first transistor 314 and the second transistor 316 are coupled to the source of the fifth transistor 322, to the drain of the sixth transistor 324 and to the drain of seventh transistor 326. The fifth transistor 322 and the sixth transistor 324 are N-channel MOSFETs (nMOSFETs). Alternatively, the fifth transistor 322 and the sixth transistor 324 may be P-channel MOSFETs (pMOSFETs), N-channel field-effect transistors (FETs), N-channel insulated-gate bipolar transistors (IGBTs), N-channel junction field effect transistors (JFETs), or NPN bipolar junction transistor (BJTs).

In FIG. 3, the current steering circuitry 312 includes a seventh transistor 326 and an eighth transistor 328. The seventh transistor 326 includes a drain, a source, and a gate. The eighth transistor 328 includes a drain, a source, and a gate. The gate of the seventh transistor 326 is coupled to the output of the window comparator 306. The gate of the eighth transistor 328 is coupled to the output of the logic gate 308. The sources of the seventh transistor 326 and the eighth transistor 328 are coupled to a supply voltage (Vdd) through a second current source 332. The drain of the seventh transistor 326 is coupled to the sources of the first transistor 314 and the second transistor 316. The drain of the eighth transistor 328 is coupled to the sources of the third transistor 318 and fourth transistor 320. The seventh transistor 326 and the eighth transistor 328 are pMOSFETs. Alternatively, the seventh transistor 326 and the eighth transistor 328 may be P-channel FETs, P-channel IGBTs, P-channel JFETs, or PNP BJTs.

In an example first operation of the second input circuitry 300, the magnitude of the potential applied to INP and INN are equal or approximately equal. The window comparator 306 outputs a low voltage responsive to zero or approximately zero difference between INP and INN. For example, the differential voltage does not meet or exceed the input differential threshold voltage of the window comparator 306 and, thus, the window comparator 306 outputs a low voltage. The seventh transistor 326 conducts current responsive to obtaining the low voltage from the output of the window comparator 306 at the gate. The logic gate 308 outputs a high voltage responsive to obtaining the low voltage from the window comparator 306. The eighth transistor 328 does not conduct current responsive to obtaining the high voltage at the gate and, thus, is turned off.

During the example first operation, the first transistor 314 and the second transistor 316 (e.g., collectively the main input pair 302) are on and conducting current responsive to the current from the seventh transistor 326. The drains of the first transistor 314 and the second transistor 316 are coupled to a first stage of an amplifier (e.g., the first stage circuitry 104 of the amplifier circuitry 100 of FIG. 1). Therefore, the first stage of the amplifier obtains a current from the main input pair 302.

In an example second operation, INP has a greater value than INN and, thus, there is an input differential at the main input pair 302. When the input differential is greater than the input differential threshold voltage, the window comparator 306 causes the source follower circuitry 310 and the current steering circuitry 312 to turn off the main input pair 302 and turn on the auxiliary input pair 304. For example, the window comparator 306 triggers in response to the difference between INP and INN crossing the input differential threshold voltage. The output of the window comparator 306 goes high. The seventh transistor 326 turns off (e.g., stops conducting current) responsive to the high output of the window comparator 306 and, thus, the main input pair 302 stops conducting current. The source follower circuitry 310 ensures that the sources of the first transistor 314 and second transistor 316 do not float to a voltage that is high enough for degradation (e.g., aging) when the seventh transistor 326 stops conducting current. For example, the source follower circuitry 310 forces the potential at the sources of the first transistor 314 and second transistor 316 to ground and/or to a low voltage.

In the example second operation, the logic gate 308 outputs a logic low in response to the high output of the window comparator 306. The eighth transistor 328 turns on and, thus, the auxiliary input pair 304 (e.g., the third transistor 318 and the fourth transistor 320) turns on and begins to conduct current. The drains of the third transistor 318 and the fourth transistor 320 are coupled to the first stage of an amplifier (e.g., the first stage circuitry 104 of the amplifier circuitry 100 of FIG. 1). Therefore, the first stage of the amplifier obtains a current from the auxiliary input pair 304 while the main input pair 302 avoids the negative effects of differential input voltage. The auxiliary input pair 304 thus degrades over time while the main input pair 302 does not degrade.

FIG. 4 is a schematic diagram of an example window comparator 400 to compare input signals of amplifier circuitry (e.g., amplifier circuitry 100). In this example, the window comparator 400 may be used to implement the window comparator 306 of FIG. 3. Additionally and/or alternatively, the window comparator 400 may be implemented by any comparator or amplifier circuitry to monitor the input signals. The window comparator 400 includes an example first transistor 402, an example second transistor 404, an example third transistor 406, an example fourth transistor 408, an example fifth transistor 410, an example sixth transistor 412, an example seventh transistor 414, an example eighth transistor 416, an example first resistor 418, an example second resistor 420, an output stage 422, and an example capacitor 424.

The first transistor 402, second transistor 404, third transistor 406, fourth transistor 408, fifth transistor 410, sixth transistor 412, seventh transistor 414, and eighth transistor 416 are pMOSFETs. Alternatively, first transistor 402, second transistor 404, third transistor 406, fourth transistor 408, fifth transistor 410, sixth transistor 412, seventh transistor 414, and eighth transistor 416 may be P-channel FETs, P-channel IGBTs, P-channel JFETs, or PNP BJTs.

In FIG. 4, the first transistor 402 includes a drain, a source, and a gate. The second transistor 404 includes a drain, a source, and a gate. The third transistor 406 includes a drain, a source, and a gate. The fourth transistor 408 includes a drain, a source, and a gate. The fifth transistor 410 includes a drain, a source, and a gate. The sixth transistor 412 includes a drain, a source, and a gate. The seventh transistor 414 includes a drain, a source, and a gate.

The gate of the first transistor 402 is configured to receive and/or obtain a second input signal, INN and the gate of the second transistor 404 is configured to receive and/or obtain a first input signal, INP. The sources of the first transistor 402 and second transistor 404 are coupled to a first terminal of a first current source 426. A second terminal of the first current source 426 is coupled to a supply voltage (AVDD) 428. The drain of the first transistor 402 is coupled to the source of the third transistor 406. The drain of the second transistor 404 is coupled to the source of the fourth transistor 408. The gate of the third transistor 406 is configured to receive and/or obtain the first input signal, INP. The gate of the fourth transistor 408 is configured to receive and/or obtain the second input signal, INN. The drain of the third transistor 406 is coupled to the source of the eighth transistor 416 and is coupled to the drain of the fourth transistor 408 at node A. The drains of the third transistor 406 and the fourth transistor 408 are coupled to the source of the eighth transistor at node A. The drain of the first transistor 402 is coupled to the first resistor 418 and the drain of the second transistor 404 is coupled to the second resistor 420. The first resistor 418 is coupled to the source of the fifth transistor 410 and the second resistor 420 is coupled to the source of the sixth transistor 412. The gate of the fifth transistor 410 is configured to receive and/or obtain the second input signal, INN. The gate of the sixth transistor 412 is configured to receive and/or obtain the first input signal, INP. The drain of the fifth transistor 410 is coupled to the source of the seventh transistor 414, to the drain of the sixth transistor 412 and to the source of the seventh transistor 414, at node B. The drain of the eighth transistor 416 is coupled to a first input of the output stage 422. The drain of the seventh transistor 414 is coupled to a second input of the output stage 422. The output of the output stage 422 is coupled to the capacitor 424 and to an input of a logic gate (e.g., logic gate 308 of FIG. 3).

The output stage 422 includes a ninth transistor 430, a third resistor 432, a tenth transistor 434, a fourth resistor 436, an eleventh transistor 438, a twelfth transistor 440, a thirteenth transistor 442, a fourteenth transistor 444, a second current source 446, a fifteenth transistor 448, a sixteenth transistor 450, a seventeenth transistor 452, an eighteenth transistor 454, a nineteenth transistor 456, a twentieth transistor 458, a twenty-first transistor 460, and a twenty-second transistor 462.

In FIG. 4, the ninth transistor 430, the tenth transistor 434, the eleventh transistor 438, the twelfth transistor 440, the thirteenth transistor 442, the fourteenth transistor 444, the sixteenth transistor 450, and the eighteenth transistor 454 are nMOSFETs. Alternatively, the ninth transistor 430, the tenth transistor 434, the eleventh transistor 438, the twelfth transistor 440, the thirteenth transistor 442, the fourteenth transistor 444, the sixteenth transistor 450, and the eighteenth transistor 454 may be pMOSFETs, N-channel FETs, N-channel IGBTs, N-channel JFETs, or NPN BJTs.

In FIG. 4, the fifteenth transistor 448, the seventeenth transistor 452, the nineteenth transistor 456, the twentieth transistor 458, the twenty-first transistor 460, and the twenty-second transistor 462 are pMOSFETs. Alternatively, the fifteenth transistor 448, the seventeenth transistor 452, the nineteenth transistor 456, the twentieth transistor 458, the twenty-first transistor 460, and the twenty-second transistor 462 may be nMOSFETs, P-channel FETs, P-channel IGBTs, P-channel JFETs, or PNP BJTs.

In FIG. 4, the ninth transistor 430 includes a drain, source, and gate, and the tenth transistor 434 includes a drain, source, and gate. The source of the ninth transistor 430 is coupled to the drain of the seventh transistor 414 and to the third resistor 432. The source of the tenth transistor 434 is coupled to the drain of the eighth transistor 416 and to the fourth resistor 436. The gates of the ninth transistor 430 and tenth transistor 434 are coupled together. The drain of the tenth transistor 434 is coupled to gates of the ninth transistor 430 and tenth transistor 434. In this example, the ninth transistor 430 and the tenth transistor 434 convert a differential signal to a single ended output. For example, the ninth transistor 430 and the tenth transistor 434 make up a current mirror that reflects a first input (i2) at an output (e.g., at the drain of the ninth transistor 430) while combining that first input (i2) with a second input (i1) at the output.

In FIG. 4, the eleventh transistor 438 includes a drain, source, and gate, and the twelfth transistor 440 includes a drain, source, and gate. The gate of the eleventh transistor 438 is coupled to the drain of the ninth transistor 430. The source of the eleventh transistor 438 coupled to the drain of the twelfth transistor 440. The eleventh transistor 438 and the twelfth transistor 440 make up hysteresis in the output stage 422. Hysteresis provides a small positive feedback at the gates of the fifteenth transistor 448 and the sixteenth transistor 450, to ensure that there is a low probability of the window comparator 400 randomly toggling between two states when the difference between the inputs (INN and INP) approach the threshold point. For example, when the two inputs (INN and INP) are close to a transition point (e.g., a point where the window comparator 400 toggles from low to high or high to low), the output of the window comparator 400 may rapidly switch states. In some examples, this is due to small amounts of noise on the input signals, which are amplified by a gain (e.g., an open loop gain) of the window comparator 400, causing the output to briefly bounce back and forth. Therefore, a response of the window comparator 400 is improved by adding hysteresis (e.g., through configuration of the eleventh transistor 438 and the twelfth transistor 440).

In FIG. 4, the thirteenth transistor 442 includes a drain, source, and gate, and the fourteenth transistor 444 includes a drain, source, and gate. The gate of the thirteenth transistor 442 is coupled to the gate of the twelfth transistor 440 and to the gate of the fourteenth transistor 444. The drain of the thirteenth transistor 442 is coupled to the second current source 446 and to the gates of the thirteenth transistor 442 and fourteenth transistor 444. The thirteenth transistor 442 and the fourteenth transistor 444 make up a current mirror. For example, thirteenth transistor 442 and the fourteenth transistor 444 form a current mirror that provides a hysteresis bias current for the eleventh transistor 438 and the twelfth transistor 440.

In FIG. 4, the fifteenth transistor 448 includes a drain, source, and gate, and the sixteenth transistor 450 includes a drain, source, and gate. The gates of the fifteenth transistor 448 and the sixteenth transistor 450 are coupled to the drain of the ninth transistor 430. Additionally, the drain of the eleventh transistor 438 is coupled to the gates of the fifteenth transistor 448 and the sixteenth transistor 450 and, thus, to the drain of the ninth transistor 430. The drains of the fifteenth transistor 448 and the sixteenth transistor 450 are coupled together. The source of the fifteenth transistor 448 is coupled to a voltage V_low464. The source of the sixteenth transistor 450 is coupled to the drain of the fourteenth transistor 444. The fifteenth transistor 448 and the sixteenth transistor 450 make up a first inverter. The first inverter (e.g., configured through the fifteenth transistor 448 and the sixteenth transistor 450) enhances a slew-rate of the window comparator 400. The slew-rate is a maximum rate of change of the comparator output voltage. An enhanced slew-rate is a quick rate of change (e.g., quickly changes states).

In FIG. 4, the seventeenth transistor 452 includes a drain, source, and gate, and the eighteenth transistor 454 includes a drain, source, and gate. The gates of the seventeenth transistor 452 and the eighteenth transistor 454 are coupled to the drains of the fifteenth transistor 448 and the sixteenth transistor 450 (e.g., an output of the first inverter). The drains of the seventeenth transistor 452 and the eighteenth transistor 454 are coupled together and to the capacitor 424. The seventeenth transistor 452 and the eighteenth transistor 454 make up a second inverter. The second inverter ensures that a correct state is output by the comparator. For example, the second inverter (e.g., configured through the seventeenth transistor 452 and the eighteenth transistor 454) obtains a state from the first inverter and inverts that state back to the preceding state.

In FIG. 4, the nineteenth transistor 456 includes a drain, source, and gate, the twentieth transistor 458 includes a drain, source, and gate, the twenty-first transistor 460 includes a drain, source, and gate, and the twenty-second transistor 462 includes a drain, source, and gate. The drain of the nineteenth transistor 456 is coupled to the source of the seventeenth transistor 452. The source of the nineteenth transistor 456 is coupled to the drain of the twentieth transistor 458. The gates of the nineteenth transistor 456, the twentieth transistor 458, the twenty-first transistor 460, and the twenty-second transistor 462 are coupled together and are configured to receive a fixed biased voltage to set the required current through those transistors. The sources of the twentieth transistor 458, the twenty-first transistor 460, and the twenty-second transistor 462 are coupled to the voltage V_low464. The drain of the twenty-first transistor 460 is coupled to the drain of the tenth transistor 434. The drain of the twenty-second transistor 462 is coupled to the drain of the ninth transistor 430. Therefore, the drain of the twenty-second transistor 462 is also coupled to the gate and drain of the eleventh transistor 438 and to the gates of the fifteenth transistor 448 and the sixteenth transistor 450.

In FIG. 4, the seventh transistor 414 and the eighth transistor 416 are protection devices. For example, the gate voltages of the seventh transistor 414 and the eighth transistor 416 are biased such that the transistors 414, 416 protect the third transistor 406, the fourth transistor 408, the fifth transistor 410, and the sixth transistor 412 by limiting their drain voltages. In some examples, the gates of the seventh transistor 414 and the eighth transistor 416 are coupled to bias circuitry (not shown). Alternatively, the gates of the seventh transistor 414 and the eighth transistor 416 are coupled to a supply voltage (not shown) that biases the transistors 414, 416. For example, the gates of the seventh transistor 414 and the eighth transistor 416 may be configured to obtain a voltage that keeps the transistors 414, 416 on (e.g., conducting). Additionally and/or alternatively, the gates of the seventh transistor 414 and the eighth transistor 416 are biased by a voltage that is dependent on the input voltage (e.g., INN and INP). For example, the gates of the seventh transistor 414 and the eighth transistor 416 obtain a voltage, corresponding to and/or dependent on INN and INP, directly or from a level shifter (e.g., such as the source follower circuitry 310 of FIG. 3). In some examples, the window comparator 400 does not require protection and, therefore, the seventh transistor 414 and eighth transistor 416 are not included in the window comparator 400. In such an example, node A is coupled directly to the first input of the output stage 422 and node B is coupled directly to the second input of the output stage 422.

There are two possible paths for the current to flow from the first transistor 402 and two possible paths for current to flow from the second transistor 404 (e.g., four current paths in total) depending on the operating mode of the amplifier circuitry. The first two current paths described herein are when amplifier circuitry is operating in a regulated mode (e.g., in a mode where the voltage potential of INN and INP are equal or approximately equal). The first path current can flow through is from the first transistor 402 through the third transistor 406. Current conducting through the first transistor 402 flows through the third transistor 406 responsive to the voltage magnitude at INN being less than a comparator threshold different than the voltage magnitude at INP (e.g., when the amplifier circuitry is operating in a regulated mode). The first path (e.g., from the source of the first transistor 402 to the drain of the third transistor 406 to node A) is the main current path (referred to as the “main current path”). For example, during a regulated condition, current flows from the first transistor 402 through the first main current path.

The second path (referred to as the “second main current path”) for current to flow, during a regulated condition, is from the second transistor 404 through the fourth transistor 408 to node A. The first main current path and the second main current path are shorted at node A and, thus, the current through both the first main current path and the second main current path are summed at node A. During the example first operation of the window comparator 400, i2 is greater than it responsive to the voltage potentials of INP and INN having approximately the same value. The output of the window comparator 400 is pulled to ground responsive to i2 being greater than it.

For example, when i₂is greater than i₁, the ninth transistor 430 demands (e.g., attempts to sink) more current than is available (e.g., than is provided by the twenty-second transistor 462). For example, the current through the ninth transistor 430 is equivalent to the current through the twenty-second transistor 462 (I_pmos) plus the difference between i₁and i₂times a value ‘K’ (e.g., I_pmos+K*(i₂−i₁)), where ‘K’ is a value less than one. As such, a potential at node C (e.g., a node located at the coupling point of the drain of the ninth transistor 430 and the gates of the fifteenth transistor 448 and the sixteenth transistor 450) goes to logic ‘0’. The first inverter (e.g., the configuration of transistors 448 and 450) obtains the logic ‘0’ and inverts the logic ‘0’ to a logic ‘1.’ Subsequently, the second inverter (e.g., the configuration of transistors 452 and 454) obtains the logic ‘1’ and inverts it back to logic ‘0’ at the output of the window comparator 400.

The capacitor 424 ensures that the window comparator 400 turns on slowly in the presence of a high differential input voltage but turns off quickly when the input voltages come close together.

In an example second operation of the window comparator 400, the amplifier circuitry is operating in an unregulated mode (e.g., the voltage potential of INN is less than the voltage potential of INP by a value greater than the comparator threshold voltage). As described above, there are four possible paths for current to flow. The first two paths are associated with a regulated mode. The second two paths, described below, are associated with an unregulated mode of the amplifier circuitry. The third possible path (referred to as the “first differential current path”) for current to flow in the window comparator 400 is from the first transistor 402 through the fifth transistor 410, responsive to the magnitude of the potential at INN being more than a comparator threshold value less than the magnitude of the potential at INP. Current flows through the fifth transistor 410 responsive to the gate-to-source voltage of the fifth transistor 410 meeting/exceeding the threshold voltage of fifth transistor 410, which occurs when the differential voltage exceeds the threshold voltage set by the voltage drop across the first resistor 418. The fifth transistor 410 steers the current to the seventh transistor 414 responsive to the voltage at the gate being less than the voltage at the source. In this example, current i₁is greater than the current i₂. The output voltage of the window comparator 400 goes high responsive to current it being greater than current i₂.

For example, when i₂is less than i₁, the current through ninth transistor 430 is less than the current provided by the twenty-second transistor 462, causing the potential at node C to be logic ‘1.’ The first inverter (e.g., the configuration of transistors 448 and 450) obtains the logic ‘1’ and inverts the logic ‘1’ to a logic ‘0.’ Subsequently, the second inverter (e.g., the configuration of transistors 452 and 454) obtains the logic ‘0’ and inverts it back to logic ‘1’ at the output of the window comparator 400.

In an example third operation of the window comparator 400, the amplifier circuitry is operating in an unregulated mode (e.g., the voltage potential of INP is less than the voltage potential of INN by a value greater than the comparator threshold voltage). The fourth possible path (referred to as the “second differential current path”) for current to flow in the window comparator 400 is from the second transistor 404 through the sixth transistor 412. For example, current conducting through the second transistor 404 flows through the sixth transistor 412 responsive to the magnitude of the potential at INP being more than a comparator threshold value less than the magnitude of the potential at INN. Current flows through the sixth transistor 412 responsive to the gate-to-source voltage of the sixth transistor 412 meeting/exceeding the threshold voltage of sixth transistor 412. The gate-to-source voltage meets the threshold gate-to-source voltage responsive the differential voltage (e.g., the voltage difference between the magnitude of the voltage at INP and the magnitude of the voltage at INN) exceeding the threshold voltage set by the voltage drop across the second resistor 420. The sixth transistor 412 steers the current to the seventh transistor 414 responsive to the voltage at the gate being less than the voltage at the source. In this example, current i₁is greater than the current i₂. The output voltage of the window comparator 400 goes high responsive to current i₁being greater than current i₂.

In this description, the term “and/or” (when used in a form such as A, B and/or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A with B and with C. Also, as used herein, the phrase “at least one of A or B” (or “at least one of A and B”) refers to implementations including any of: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

Example methods, apparatus and articles of manufacture described herein improve performance specifications of amplifiers are disclosed herein. Further examples and combinations thereof include the following:

Example 1 includes an apparatus comprising a first amplifier stage (104) having a first stage input, a first input pair (302) having a first input and a first output coupled to the first stage input, a second input pair (304) having a second input and a second output, current steering circuitry (312) having a third input, a fourth input, a third output, and a fourth output, the third output coupled to the first input and the fourth output coupled to the second input, source follower circuitry (310) having a fifth input and a fifth output, the fifth output coupled to the first input, and a comparator (306) having a sixth output coupled to the fifth input.

Example 2 includes the apparatus of example 1, wherein the first input pair (302) comprises a first transistor (314) having a first source coupled to the third output, and a second transistor (316) having a second source coupled to the third output and to the first source.

Example 3 includes the apparatus of example 1, wherein the second input pair (304) comprises a first transistor (318) having a first source coupled to the fourth output, and a second transistor (320) having a second source coupled to the fourth output and to the first source.

Example 4 includes the apparatus of example 1, wherein the current steering circuitry (312) comprises a first transistor (326) having a first drain and a first gate, the first drain coupled to the first input and the first gate coupled to the sixth output, and a second transistor (328) having a second drain and a second gate, the second drain coupled to the second input.

Example 5 includes the apparatus of example 4, wherein the apparatus further includes a logic gate (308) having a sixth input and a sixth output, the sixth input coupled to the fifth output and the sixth output coupled to the second gate of the second transistor (328).

Example 6 includes the apparatus of example 1, wherein the source follower circuitry (310) comprises a first transistor (322) having a first source and a first gate, the first source coupled to the first input and the first gate configured to receive the smaller of a first signal or a second signal, and a second transistor (324) having a second gate and a first drain, the second gate coupled to the fifth output and the first drain coupled to the first source of the first transistor (322).

Example 7 includes the apparatus of example 1, wherein the first input pair (302) comprises a first transistor (314) having a first source and a first gate, the first source coupled to the third output and the first gate configured to receive a first signal (INP), and a second transistor (316) having a second source and a second gate, the second source coupled to the third output and to the first source, and the second gate configured to receive a second signal (INN) that is equivalent to the first signal (INP), the second input pair (304) comprises a third transistor (318) having a third source and a third gate, the third source coupled to the fourth output and third gate configured to receive the first signal (INP), and a fourth transistor (320) having a fourth source and a fourth gate, the fourth source coupled to the fourth output and the third source, the fourth gate configured to receive the second signal (INN), and the current steering circuitry (312) comprises a fifth transistor (326) having a fifth drain and a fifth gate, the fifth drain coupled to the first source and the second source, the fifth gate coupled to the sixth output, and a sixth transistor (328) having a sixth drain and a sixth gate, the sixth drain coupled to the third source and to the fourth source.

Example 8 includes the apparatus of example 7, further including a seventh transistor (322) having a seventh source and a seventh gate, the seventh source coupled to the first source and to the second source, the first gate configured to receive the smaller of the first signal (INP) or the second signal (INN), and an eighth transistor (324) having an eighth gate and an eighth drain, the eighth gate coupled to the fifth output and the eighth drain coupled to the seventh source.

Example 9 includes an amplifier (100) comprising input circuitry including a main input pair (302) having a first input, a first output, and a second output, an auxiliary input pair (304) having a second input, a third output, and a fourth output, the third output coupled to the first output and the fourth output coupled to the second output, and a comparator (306) having a fifth output coupled to the first input and to the second input via a current steering circuit (312), the comparator (306) to control operation of the main input pair (302) and the auxiliary input pair (304), first stage circuitry (104) having first stage input and a first stage output, the first stage input coupled to the first output, the second output, the third output, and the fourth output, second stage circuitry (106) having a second stage input and a second stage output, the second stage input coupled to the first stage output.

Example 10 includes the amplifier of example 9, wherein the current steering circuit (312) includes a third input, a fourth input, a sixth output, and a seventh output, the third input coupled to the fifth output of the comparator (306), the fourth input adapted to be coupled to the fifth output of the comparator (306), the sixth output coupled to the first input, and the seventh output coupled to the second input.

Example 11 includes the amplifier of example 9, wherein the input circuitry further comprises source follower circuitry (