Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiment or designs. The terms “at least one” and “one or more” can be understood to include any integer number greater than or equal to one, i.e., one, two, three, four, etc. The terms “a plurality” can be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, etc. The term “connection” can include both indirect “connection” and a direct “connection.”

As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrations or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. The terms “about” or “substantially” are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of the filing of the application. For example, about can include a range of ±8%, or 5%, or 2% of a given value. In another aspect, the term “about” means within 5% of the reported numerical value. In another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

Various processes are used to form a micro-chip that will packaged into an integrated circuit (IC) fall in four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etching process (either wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implant dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage.

Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, where like reference numerals refer to like elements throughout. The present invention is directed to forming an interconnect between stacked transistors, where the interconnect makes a connection between adjacent source/drains in the same cell, source/drains that are not adjacent to each other but located in the same cell, and source/drains located in different cells. The interconnect is located in a gate cut region that makes a connection between the different source/drains through the gate cut region. The interconnect can connect bottom to bottom, bottom to top, top to top, top to bottom, or bottom to bottom to top to top. The interconnect is able to make a connection between adjacent source/drains or the interconnect can make a connection between source/drains that are separated by a distance. There can be more than one interconnect connected to a group of stacked devices.

FIG. 1 illustrates a top-down view of stack devices separated by a gate cut having examples of cell interconnects, in accordance with the embodiment of the present invention. The present invention is comprised of one or more stacked devices, having a lower device and an upper device. The stacked devices are separated from adjacent stack devices by a gate cut filled with a dielectric material. FIG. 1 illustrates examples of cell interconnects that are comprised of a conductive metal, where the cell interconnects are located within the gate cut. The cell interconnect makes a connection between source/drain of the stacked devices within the same cell or between cells. The cell interconnect extends through a portion of the gate cut to form a connection between the different cells. One or more of the cell interconnects can be present in the stacked devices. Cross section X₁extends through horizontal of the stacked devices region. Cross section X₂extends through the horizontal of the gate cut, where the interconnect is at located. Cross section Y₁is perpendicular to cross section X₁and cross section X₂, where cross section Y₁is through the gate region of the stacked devices.

FIG. 2 illustrates a cross section X₁of the stacked device region after the formation of bottom source/drain 145 and a first placeholder 150, in accordance with the embodiment of the present invention. The stacked nano device includes a substrate 105, an oxide layer 110, a bottom device 112, an isolation layer 120, an upper device 122, a bottom source/drain 145, and a first placeholder 150.

The substrate 105 can be, for example, a material including, but not necessarily limited to, silicon (Si), silicon germanium (SiGe), Si:C (carbon doped silicon), carbon doped silicon germanium (SiGe:C), III-V, II-V compound semiconductor or another like semiconductor. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate 105. In some embodiments, the substrate 105 includes both semiconductor materials and dielectric materials. The semiconductor substrate 105 may also comprise an organic semiconductor or a layered semiconductor such as, for example, Si/SiGe, a silicon-on-insulator or a SiGe-on-insulator. A portion or the entire semiconductor substrate 105 may also be comprised of an amorphous, polycrystalline, or monocrystalline. The semiconductor substrate 105 may be doped, undoped or contain doped regions and undoped regions therein.

The bottom device 112 includes alternating layers of bottom sacrificial layer 114 and bottom nanosheets 116, and a bottom inner spacer 118 located in a spaced created by recessing of the bottom sacrificial layers 114. The bottom source/drain 145 extends from the sidewalls of the bottom nanosheets 116 into the space between sections of the bottom device 112. A first placeholder 150 is formed in the space between sections of the bottom device 112, where the first placeholder 150 is in direct contact with the bottom source/drain 145 and the bottom inner spacer 118. The first placeholder can be comprised of, for example, TiO_x. An isolation layer 120 is formed on top of the bottom device 112. The isolation layer 120 can be comprised of, for example, a dielectric material.

The bottom source/drain 145 can be for example, a n-type epitaxy, or a p-type epitaxy. For n-type epitaxy, an n-type dopant selected from a group of phosphorus (P), arsenic (As) and/or antimony (Sb) can be used. For p-type epitaxy, a p-type dopant selected from a group of boron (B), gallium (Ga), indium (In), and/or thallium (Tl) can be used. Other doping techniques such as ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, and/or any suitable combination of those techniques can be used. In some embodiments, dopants are activated by thermal annealing such as laser annealing, flash annealing, rapid thermal annealing (RTA) or any suitable combination of those techniques.

An upper device 122 is formed on top of the isolation layer 120. The upper device 122 includes alternating layers of upper sacrificial layer 124 and upper nanosheet 126, and an upper inner spacer 128 located in a spaced created by recessing of the upper sacrificial layers 124. A dummy gate 130 is formed on top of the upper device 122. A hardmask 135 is formed on top of the dummy gate 130. Upper spacer 140 are located on the sidewalls of the dummy gate 130 and the hardmask 135.

FIG. 3 illustrates a cross section X₂of the gate cut region after the formation of bottom source/drain 145 and a first placeholder 150, in accordance with the embodiment of the present invention. The gate cut region includes the substrate 105, the oxide layer 110, the dummy gate 130, the hardmask 135, the upper spacer 140, and the first placeholder 150. The columns of the dummy gate 130, hardmask 135, and the upper spacer 140 are separated by the first placeholder 150.

FIG. 4 illustrates a cross section Y₁of the gate region after the formation of bottom source/drain and a first placeholder, in accordance with the embodiment of the present invention. The gate region includes the substrate 105, the oxide layer 110, the bottom device 112, the isolation layer 120, the upper device 122, the dummy gate 130, and the hardmask 135. The dummy gate 130 includes the stack of the bottom device 112, the isolation layer 120, and the upper device 122.

FIGS. 5 and 6 illustrate the process stage after patterning the placeholder 150, and formation of a middle isolation layer 155, an upper source/drain 160 and a second placeholder 165, in accordance with the embodiment of the present invention. FIG. 5 illustrates a cross section X₁of the stacked device region after patterning the first placeholder 150, the formation of a middle isolation layer 155, an upper source/drain 160 and a second placeholder 165, in accordance with the embodiment of the present invention. A middle isolation layer 155 is formed on top of the first placeholder 150. A second placeholder 165 is formed on top of the middle isolation layer 155. The second placeholder 165 can be comprised of, for example, TiO_x.

FIG. 6 illustrates a cross section X₂of the gate cut region after patterning the first placeholder 150, and the formation of a middle isolation layer 155, and a second placeholder 165, in accordance with the embodiment of the present invention. A portion of the first placeholder 150 is removed by lithography and etching process. The arrangement of the first placeholder 150, the middle isolation layer 155, and the second placeholder 165 will determine the final arrangement for the interconnect, i.e., which source/drains the interconnect will make a connection to. For example, if the interconnect will have a bottom-to-bottom, bottom-to-top, top-to-bottom, or multiple connections are determined by the arrangement of the first placeholder 150, the middle isolation layer 155, and the second placeholder 165. As illustrated by FIG. 6, a portion of the first placeholder 150 is removed and replaced with the middle isolation layer 155. The second placeholder 165 is formed on top of the middle isolation layer 155 and patterned by lithography and etching process so that only a portion of the second placeholder 165 remains. For example, the configuration of the first placeholder 150, the middle isolation layer 155, and the second placeholder 165 will lead to an interconnect having a bottom-to-top configuration. The configuration of the interconnect that is illustrated by the Figures is not meant to be limiting, and different configures of the interconnect are possible.

FIGS. 7 and 8 illustrate the process stage after formation of an interlayer dielectric 170, in accordance with the embodiment of the present invention. FIG. 7 illustrates a cross section X₁of the stacked device region after the formation of an interlayer dielectric 170, in accordance with the embodiment of the present invention. FIG. 8 illustrates a cross section X₂of the gate cut region after the formation of an interlayer dielectric, in accordance with the embodiment of the present invention. An interlayer dielectric 170 is formed on top of the second placeholder 165. Furthermore, the interlayer dielectric 170 can be formed on top of the middle isolation layer 155, as illustrated by FIG. 8. When the design for the interconnect will have a top-to-top connection, then the interlayer dielectric 170 is located top of the second placeholder 165 not on top of the middle isolation layer 155 at the location of the interconnect.

FIGS. 9, 10 and 11 illustrates a process stage after gate patterning is performed by a conventional lithography and etching process, which selectively etching the dummy gate 130, upper spacer 140, selective to interlayer dielectric 170. FIG. 9 illustrates a cross section X₁of the stacked device region after the formation of a gate cut, in accordance with the embodiment of the present invention. FIG. 10 illustrates a cross section X₂of the gate cut region after the formation of the gate cut 175, in accordance with the embodiment of the present invention. A lithography layer (not show) is formed on top of the interlayer dielectric 170 and on top of the dummy gate 130. The underlying layers are patterned and the dummy gate 130 and the upper spacer 140 are removed. Columns comprised of the first placeholder 150, the middle isolation layer 155, the second placeholder 165, and the interlayer dielectric 170 remain.

FIG. 11 illustrates a cross section Y₁of the gate region after the formation of the gate cut 175, in accordance with the embodiment of the present invention. A lithography layer (not shown) is formed on top of the dummy gate 130 and the dummy gate 130 is patterned. Gate cuts 175 are formed in the dummy gate 130.

FIG. 12 illustrates a process stage after formation of a selective dielectric liner 180 over the exposed surfaces of dummy gate, followed by an anisotropic etching process to remove any horizontal portions of dielectric liner 180. FIG. 12 illustrates a cross section Y₁of the gate region after the formation of the selective dielectric liner 180, in accordance with the embodiment of the present invention. A selective dielectric liner 180 is formed on the exposed surfaces of dummy gate 130 and etched back so that the selective dielectric liner 180 remains on the sidewalls of the gate cut 175.

FIGS. 13, 14 and 15 illustrate a process stage after the formation of a dielectric fill layer 185, in accordance with the embodiment of the present invention. FIG. 13 illustrates a cross section X₁of the stacked device region after the formation of a dielectric fill layer 185, in accordance with the embodiment of the present invention. FIG. 14 illustrates a cross section X₂of the gate cut region after the formation of a dielectric fill layer 185, in accordance with the embodiment of the present invention. FIG. 15 illustrates a cross section Y₁of the gate region after the formation of a dielectric fill layer 185, in accordance with the embodiment of the present invention. A dielectric fill layer 185 is formed on the buried oxide layer 110 and extends up the sidewalls of the columns that contains the first placeholder 150, the middle isolation layer 155, the second placeholder 165, and the interlayer dielectric 170. The dielectric fill layer 185 further fills the gate cut 175 and the dielectric fill layer 185 is in contact with selective dielectric liner 180.

FIGS. 16, 17 and 18 illustrate a process stage after dummy gate 130 and sacrificial SiGe (bottom sacrificial layer 114, and upper sacrificial layer 124) is removed, followed by gate 190, and gate cap 195 formation. FIG. 16 illustrates a cross section X₁of the stacked device region after the formation of the gate 190, in accordance with the embodiment of the present invention. FIG. 17 illustrates a cross section X₂of the gate cut region after the formation of a gate 190, in accordance with the embodiment of the present invention. FIG. 18 illustrates a cross section Y₁of the gate region after the formation of a gate 190, in accordance with the embodiment of the present invention. The bottom sacrificial layers 114, the upper sacrificial layers 124, and the dummy gate 130 are removed creating an empty space. The gate 190 is formed by filling empty space with the gate material. The gate 190 can be comprised of, for example, a gate dielectric liner, such as high-k dielectric like HfO₂, ZrO₂, HfL_aO_x, etc., and work function layers, such as TiN, TiAlC, TiC, etc., and conductive metal fills, like W. A gate cap 195 is formed on top of the gate 190 after gate CMP and gate recess.

FIGS. 19, 20 and 21 illustrate a process stage after formation of source/drain contact openings and local interconnect contact openings, by litho and etching process. FIG. 19 illustrates a cross section X₁of the stacked device region after the formation of a contact opening 197, in accordance with the embodiment of the present invention. A portion of the interlayer dielectric 170 is removed to form a contact opening 197. FIG. 20 illustrates a cross section X₂of the gate cut region after the formation of a first interconnect opening 198, in accordance with the embodiment of the present invention. The first interconnect opening 198 is formed by removing a portion of the dielectric fill layer 185 located between the columns comprised of the first placeholder 150, the middle isolation layer 155, the second placeholder 165, and the interlayer dielectric 170. FIG. 21 illustrates a cross section Y₁of the gate region after the formation of a first interconnect opening 198, in accordance with the embodiment of the present invention. The dielectric fill layer 185 located within a portion of the gate cut 175 is removed to create the interconnect opening 198. The etch process of the dielectric fill layer 185 can be selective to the selective dielectric liner 180, such that local interconnect 212 is isolated from the gate 190.

FIGS. 22, 23, and 24 illustrate a process stage after the removal of the first placeholder 150 and the second placeholder 165, in accordance with the embodiment of the present invention. FIG. 22 illustrates a cross section X₁of the stacked device region after the removal of the first placeholder 150 and the second placeholder 165, in accordance with the embodiment of the present invention. FIG. 23 illustrates a cross section X₂of the gate cut region after the removal of the first placeholder 150 and the second placeholder 165, in accordance with the embodiment of the present invention. FIG. 24 illustrates a cross section Y₁of the gate region after the removal of the first placeholder 150 and the second placeholder 166, in accordance with the embodiment of the present invention. The first placeholder 150 and the second placeholder 165 are selectively removed to create contact opening 200 and a second interconnected opening 200A. As illustrated by FIG. 23, the second interconnect opening 200A is connected to the interconnect opening 198, thus forming a connection with the bottom source/drain 145 and the interconnect opening 198. A third interconnect opening 200B is also connected to the interconnect opening 198. The third interconnect opening 200B will be connected to an upper source/drain 160 (not show) of a different cell. As seen by FIG. 22, the contact opening 197 is connected to one of the second interconnect opening 200. The layout where the first placeholder 150 and the second placeholder 165 are located will determine where the second interconnect opening 200A, or third interconnect opening 200B, etc., will be located. These locations will determine to which source/drain 145, 160 the interconnect will be connected to.

FIGS. 25, 26 and 27 illustrate a process stage after metallization of contacts and local interconnects. FIG. 25 illustrates a cross section X₁of the stacked device region after the formation of the contact 210, in accordance with the embodiment of the present invention. The contact opening 197 and the second interconnect opening 200A are filled in with a conductive metal to form the contact 210 and the interconnect arm 214.

FIG. 26 illustrates a cross section X₂of the gate cut region after the formation of the interconnect 212, in accordance with the embodiment of the present invention. FIG. 27 illustrates a cross section Y₁of the gate region after the formation of the interconnect 212, in accordance with the embodiment of the present invention. The interconnect 212 is located within the dielectric fill layer 185. The interconnect 212 has a center section located within the dielectric fill layer 185 and has an interconnect arm 214 to connect to a bottom source/drain 145. The interconnect 212 has a second interconnect arm 216 connected to an upper source/drain 160. The example interconnect illustrated by FIG. 26, has an interconnect arm 214 which connects to a bottom source/drain 145 of a first cell and has a second interconnect arm 216 that connects to an upper source/drain 160 of a second cell.

FIGS. 28 to 35 illustrates a cross section X₂of the gate cut region after the formation of the plurality of different interconnect configurations, in accordance with the embodiment of the present invention. FIGS. 28 and 32 illustrate different configurations for the interconnect 217, 222 to form a connection between two upper source/drains 160 in two different cells. FIGS. 29 and 33 illustrate different configurations for the interconnect 218, 224 to form a connection between two bottom source/drains 145 in two different cells. FIGS. 30 and 34 illustrate different configurations for the interconnect 219, 226 to form a connection between an upper source/drain 160 and a bottom source/drain 145 in two different cells. The configuration represented in FIGS. 30 and 34 is a mirror of the configuration represented in FIG. 26. FIGS. 31 and 35 illustrate different configurations for the interconnect 220, 228 to form a connection between two upper source/drains 160 and two bottom source/drains 145 in at least two different cells.

FIG. 36 illustrates a top-down view of stack devices separated by a gate cut, in accordance with the embodiment of the present invention. The present invention is comprised one or more stacked devices, having a lower device and an upper device. The stacked devices are flipped over to allow for the backside processing of the devices. The stacked devices are separated from adjacent stack devices by a gate cut filled with a dielectric material. FIG. 36 illustrates only a single interconnect, but the stacked devices can have one or more of the interconnects can be present in the stacked devices. Cross section X_Aextends through horizontal of the stacked devices region. Cross section X_Bextends through the horizontal of the gate cut. Cross section Y_Ais perpendicular to cross section X_Aand cross section X_B, where cross section Y_Ais through the gate region of the stacked devices. Cross section Y_Bis perpendicular to cross section X_Aand cross section X_B, where cross section Y_Bis through the source/drain region of the stacked devices.

FIGS. 37, 38, 39 and 40 illustrate the process stage after bottom and upper source/drain regions are formed. FIG. 37 illustrates a cross section X_Aof the stacked device region after the formation of bottom and upper source/drain 345, 355 and the gate 330, in accordance with the embodiment of the present invention. The stacked devices include a substrate 305, an oxide layer 310, a bottom device 312, an isolation layer 320, an upper device 322, a gate 330, a gate cap 335, an upper spacer 340, inner spacers 318, a bottom source/drain 345, a middle isolation layer 350, an upper source/drain 355, and an interlayer dielectric 360.

The substrate 305 can be, for example, a material including, but not necessarily limited to, silicon (Si), silicon germanium (SiGe), Si:C (carbon doped silicon), carbon doped silicon germanium (SiGe:C), III-V, II-V compound semiconductor or another like semiconductor. In addition, multiple layers of the semiconductor materials can be used as the semiconductor material of the substrate 305. In some embodiments, the substrate 305 includes both semiconductor materials and dielectric materials. The semiconductor substrate 305 may also comprise an organic semiconductor or a layered semiconductor such as, for example, Si/SiGe, a silicon-on-insulator or a SiGe-on-insulator. A portion or the entire semiconductor substrate 305 may also be comprised of an amorphous, polycrystalline, or monocrystalline. The semiconductor substrate 305 may be doped, undoped or contain doped regions and undoped regions therein.

The bottom device 312 includes a plurality of nanosheets 315, an inner spacer 318, and the gate 330. The upper device 322 includes a plurality of nanosheets 325, the inner spacer 318, and the gate 330. The gate 330 can be comprised of, for example, a gate dielectric liner, such as high-k dielectric like HfO₂, ZrO₂, HfL_aO_x, etc., and work function layers, such as TiN, TiAlC, TiC, etc., and conductive metal fills, like W. The gate cap 335 is located on top of the gate 330.

The upper source/drain 355 and the bottom source/drain 350 can be for example, a n-type epitaxy, or a p-type epitaxy. For n-type epitaxy, an n-type dopant selected from a group of phosphorus (P), arsenic (As) and/or antimony (Sb) can be used. For p-type epitaxy, a p-type dopant selected from a group of boron (B), gallium (Ga), indium (In), and/or thallium (Tl) can be used. Other doping techniques such as ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, infusion doping, liquid phase doping, solid phase doping, and/or any suitable combination of those techniques can be used. In some embodiments, dopants are activated by thermal annealing such as laser annealing, flash annealing, rapid thermal annealing (RTA) or any suitable combination of those techniques. The interlayer dielectric 360 is located on top of the upper source/drain 355.

FIG. 38 illustrates a cross section X_Bof the gate cut region after the formation of bottom and upper source/drain 345, 355 and the gate 330, in accordance with the embodiment of the present invention. FIG. 38 illustrates a plurality of columns that includes the gate 330, the gate cap 335, and the upper spacer 340. The interlayer dielectric 360 is located between the columns.

FIG. 39 illustrates a cross section Y_Aof the gate region after the formation of bottom and upper source/drain 345, 355 and the gate 330, in accordance with the embodiment of the present invention. The gate 330 is located all around the plurality of nanosheets 316, 326, and all around the isolation layer 320.

FIG. 40 illustrates a cross section Y_Bof the source/drain region after the formation of bottom and upper source/drain 345, 355 and the gate 330, in accordance with the embodiment of the present invention. The bottom source/drain 345 is located on top of the oxide layer 310. The middle isolation layer 350 is located atop of the oxide layer 310 and atop of the bottom source/drain 345. The middle isolation layer 355 is located on three sides of the bottom source/drain 345. The upper source/drain 355 is located on top of the middle isolation layer 350. The interlayer dielectric 360 is located on top of the middle isolation layer 350 and on top of the upper source/drain 355. The interlayer dielectric 360 is located on three sides of the upper source/drain 355.

FIGS. 41, 42, 43 and 44 illustrate the process stage after gate cut 370 formation. FIG. 41 illustrates a cross section X_Aof the stacked device region after the formation of the gate cut 370, in accordance with the embodiment of the present invention. FIG. 42 illustrates a cross section X_Bof the gate cut region after the formation of the gate cut 370, in accordance with the embodiment of the present invention. As illustrated by FIG. 42, the columns of the gate 330, the gate cap 335, and the upper spacer 340 are removed. The interlayer dielectric 360 is also removed. The removal of these layers creates an empty space, where a dielectric fill is deposited to fill this space. The gate cut 370 is comprised of this dielectric fill material.

FIG. 43 illustrates a cross section Y_Aof the gate region after the formation of the gate cut 370, in accordance with the embodiment of the present invention. A trench is cut into the gate 330 and the gate cap 335 to create the space for the gate cut 370. A dielectric liner 365 is formed on the exposed surfaces and etched back, so that only a portion of the dielectric liner 365 remains on the sidewalls of the trench. The dielectric fill is deposited in the remaining space within the trench to form the gate cut 370.

FIG. 44 illustrates a cross section Y_Bof the source/drain region after the formation of the gate cut 370, in accordance with the embodiment of the present invention. A trench is cut into the middle isolation layer 350 and the interlayer dielectric 360 to create the space for the gate cut 370. A dielectric liner 365 is formed on the exposed surfaces and etched back, so that only a portion of the dielectric liner 365 remains on the sidewalls of the trench. The dielectric fill is deposited to fill the remaining space within the trench to form the gate cut 370.

FIGS. 45, 46, 47 and 48 illustrate the process stage after the formation of the first section of the interconnect 380, in accordance with the embodiment of the present invention. FIG. 45 illustrates a cross section X_Aof the stacked device region after the formation of the first section of the interconnect 380, in accordance with the embodiment of the present invention. FIG. 46 illustrates a cross section X_Bof the gate cut region after the formation of the first section of the interconnect 380, in accordance with the embodiment of the present invention. FIG. 47 illustrates a cross section Y_Aof the gate region after the formation of the first section of the interconnect 380, in accordance with the embodiment of the present invention. FIG. 48 illustrates a cross section Y_Bof the source/drain region after the formation of the first section of the interconnect 380, in accordance with the embodiment of the present invention. A trench is formed in the gate cut 370 by removing a portion of the gate cut 370. The first section of the interconnect 380 is formed by filling the trench in the gate cut 370 with a conductive metal.

FIGS. 49, 50, 51 and 52 illustrate the process stage after the formation of the MOL contact, 385, 386, 387, lower BEOL interconnect (M1-V0 395), additional BEOL 400, and bonding carrier wafer 405. FIG. 49 illustrates a cross section X_Aof the stacked device region after forming the second section of the interconnect 386 and forming an upper contact 385, BEOL (395 and 400), and carrier wafer 405, in accordance with the embodiment of the present invention. FIG. 50 illustrates a cross section X_Bof the gate cut region after the formation of the second section of the interconnect 386 and formation of an upper contact 385, BEOL (395 and 400), and carrier wafer 405, in accordance with the embodiment of the present invention.

An additional interlayer dielectric 363 is formed on top of the gate cap 335, the upper spacer 340, and the interlayer dielectric 360. One or more trenches are formed in the additional interlayer dielectric 363 and the interlayer dielectric 360 exposing the top surface of the upper source/drain 355. The trenches are filled with a conductive metal to form one or more upper contacts 385. One trench is filled with a conductive metal to form a second section of the interconnect 386. The second section of the interconnected 386 is in contact with the first section of the interconnect 380 as illustrated by FIG. 50. The second section of the interconnect 386 creates a direct connection between one of the upper source/drains 355 and the first section of the interconnect 380. Additional dielectric layer 390 is formed on top of the additional interlayer dielectric 363. A metal-via layer (M1-V0) 395 is formed in the dielectric layer 390 and M1-V0 395 connects to one or more upper contacts 385. The additional BEOL layer 400 is formed on top of the M1-V0 395 and a carrier wafer 405 is attached to the BEOL layer 400.

FIG. 51 illustrates a cross section Y_Aof the gate region after the formation of gate contact 387, BEOL (395 and 400), and carrier wafer 405, in accordance with the embodiment of the present invention. An additional interlayer dielectric 363 is formed on top of the gate cap 335, dielectric liner 365, gate cut 370, and the first section of the interconnect 380. One or more trenches are formed in the additional interlayer dielectric