>26 may be substantially coplanar with the side surface 28s of the hard mask 28. In another embodiment, the top surface 26t of the bottom electrode 26 is larger than the bottom surface 28b of the hard mask 28. The side surfaces 26s and 28s may not be coplanar. For example, the side surface 28s may be recessed from the side surface 26s. In yet another embodiment, the top surface 28t of the hard mask 28 may have substantially the same size as the bottom surface 32b of the middle electrode 32. The side surfaces 28s and 32s may be substantially aligned. For example, the side surface 28s of the hard mask 28 may be substantially coplanar with the side surface 32s of the middle electrode 32. In an alternative embodiment, the top surface 28t of the hard mask 28 may be smaller than the bottom surface 32b of the middle electrode 32. The side surfaces 28s and 32s may not be coplanar. For example, the side surface 28s may be recessed from the side surface 32s.

Now unit cell 100B will be described with reference to FIG. 3A. Another hard mask 34 is arranged over the middle electrode 32 and a top electrode 36 is arranged over the hard mask 34. The hard mask 34 may have a bottom surface 34b, a top surface 34t opposite the bottom surface 34b, and at least one side surface 34s. The bottom surface 34b of the hard mask 34 may be in direct contact with at least a portion of the top surface 32t of the middle electrode. The top electrode 36 may have a bottom surface 36b, a top surface 36t opposite the bottom surface 36b, and at least one side surface 36s. The bottom surface 36b of the top electrode 36 may be in direct contact with the top surface 34t of the hard mask 34. In an embodiment, the top surface 32t of the middle electrode 32 may have substantially the same size as the bottom surface 34b of the hard mask 34. The side surfaces 34s and 36s may be substantially aligned. For example, the side surface 34s of the hard mask 34 may be substantially coplanar with the side surface 36s of the top electrode 36. In another embodiment, the top surface 34t of the hard mask 34 is smaller than the bottom surface 36b of the top electrode 36. The side surfaces 34s and 36s may not be coplanar. For example, the side surface 34s may be recessed from the side surface 36s. In yet another embodiment, the side surface 34s of the hard mask may be substantially coplanar with the side surface 32s of the middle electrode 32. In an exemplary embodiment, the electrode side surfaces 26s, 32s and 36s are substantially aligned or coplanar with the hard mask side surfaces 28s and 34s. In an alternative embodiment, the hard mask surfaces 28s and 34s are recessed from electrode side surfaces 26s, 32s and 36s. As can be seen from FIG. 3A, the side surface 40s of the electrode stack 40 includes the electrode side surfaces 26s, 32s, 36s, and the hard mask side surfaces 28s, 34s. The switching layer 38 arranged over the electrode stack 40 may be in direct contact with each of the electrode side surfaces 26s, 32s and 36s and each of the hard mask side surfaces 28s and 34s. The switching layer 38 may also directly contact the top surface 36t of the top electrode 36 and include a horizontal portion 38_Hover the dielectric material 10. An interlayer dielectric material 50 may cover the switching layer 38.

Now referring to FIG. 3B which shows an exemplary simplified cross-sectional view of memory device 100 along line Y-Y′ in FIG. 1A. The top electrode 36 is coupled to and in direct contact with via 22. The top surface 36t of the top electrode 36 may be covered by switching layer 38. The bottom electrode 26 may have a length L_BE, the middle electrode may have a length L_ME, and the top electrode 36 may have a length Lm. The electrode lengths L_BE, L_MEand L_TEare substantially parallel to a first axis, which may be the X-axis as an example. In one embodiment, the length L_HM1of the hard mask 28 taken along the same axis as the lengths of the electrodes may be substantially the same as the length L_BEof the bottom electrode. The length L_BEof the bottom electrode and the length L_MEof the middle electrode may be substantially the same. For example, the length L_HM1of the hard mask 28 may be the same as the lengths L_BEand L_MEof the bottom and middle electrodes respectively. In an embodiment, the top electrode length L_TEmay not be equal to the middle electrode length L_ME. For example, the top electrode length L_TEmay be shorter than the middle electrode length L_ME. In another embodiment, the length L_HM2of the hard mask 34 taken along the same axis as the lengths of the electrodes may be substantially the same as the length L_TEof the top electrode 36. In yet another embodiment, the length L_HM2of the hard mask 34 may not be equal to the length L_MEof the middle electrode 32. The length L_HM2of the hard mask 34 may be shorter than the length L_MEof the middle electrode 32 such that a portion of the top surface 32t may be uncovered by the hard mask 34. For example, a portion of the top surface 32t is not in contact with the bottom surface 34b of the hard mask 34. In another example, the length L_HM2of the hard mask 34 may be substantially the same as the length L_MEof the middle electrode 32 with at least a portion of the top surface 32t in contact with the via 24.

Still referring to FIG. 3B, the electrode stack 40 may have at least a side surface 40s′ that is substantially parallel to the Y-axis. For example, the electrode stack 40 may have two side surfaces 40s′ which are opposite to each other. The side surface 40s′ includes the side surface 26s′ of the bottom electrode 26, the side surface 32s′ of the middle electrode 32, the side surface 36s′ of the top electrode 36, the side surface 28s′ of the hard mask 28 and side surface 34s′ of the hard mask 34. In one embodiment, at least a portion of a side surface 40s′ of the electrode stack 40 may be uncovered by the switching layer 38. For example, a side surface 36s′ of the top electrode 36 and a side surface 34s′ of the hard mask 34 may be uncovered by the switching layer 38, while the side surfaces 32s′, 28s′ and 26s′, of the middle electrode 32, the hard mask 28 and the bottom electrode 26 respectively, may be covered by and be in direct contact with the switching layer 38. In another example, a first side surface 40s′ may be covered by the switching layer 38, while another side surface 40s′ opposite to first side surface 40s′, may be partially covered by the switching layer 38.

FIGS. 4 through 6B illustrate an exemplary process for making various embodiments of the invention, such as in FIGS. 1A and 2. First referring to FIG. 4, an interconnect structure 20 in a dielectric material 10 may be provided. The interconnect structure 20 may include a via 14 formed over a terminal connection, which may be source line 12. One or more layers of interlayer dielectric material 10 are deposited to surround and electrically isolate the via 14 and source line 12 from other interconnect structures. A material removal process, such as a chemical mechanical planarization (CMP) process may be performed so that the top surface of the via 14 is substantially level with the top surface of the interlayer dielectric material 10, forming a substantially planar surface for subsequent processing. An electrode stack 40 is formed over the top surface of the via 14 and may extend horizontally to cover a portion of the dielectric material 10. The electrode stack 40 may be formed by depositing alternate layers of selected conductive materials and hard mask materials over the top surface of the via 14 and interlayer dielectric material 10. For example, a layer of conductive material selected for the bottom electrode 26 is first deposited over the top surface of via 14 and interlayer dielectric material 10, followed by a layer of hard mask material for hard mask 28, and then followed by another layer of conductive material selected for the middle electrode 32. Another layer of hard mask material for hard mask 34 is deposited over the middle electrode 32, followed by another layer of conductive material selected for the top electrode 36. The conductive materials for each of the electrodes may be deposited by physical vapor deposition (PVD), or any other suitable process. The hard mask material may include a dielectric material, such as silicon dioxide or silicon nitride, and be deposited by a suitable deposition technique such as chemical vapor deposition (CVD). The material stack comprising the alternating layers of conductive material and hard mask material may then be patterned by lithography and etching processes to define the electrode stack 40 having a side surface 40s. As part of the patterning process, another patterning hard mask layer (not shown) may be utilized together with a material removal process such as a reactive ion etching (RIE) process, and subsequently removed from the top surface 36t of the top electrode 36. The patterning hard mask may shield a portion of the alternating material stack underneath the patterning hard mask, such that the material removal process may remove conductive material and hard mask material that are unshielded by the patterning hard mask. It is understood that process limitations may result in slightly sloped sidewalls for the electrode stack 40, as well as rounded edges or corners, in certain instances. In an alternate embodiment, the electrode stack 40 may optionally undergo a further material removal process that may be tuned to achieve increased material removal in the lateral direction for the hard mask materials 28 and 34. This may result in a device structure shown in FIGS. 7A and 7B which will be described in detail later. A suitable material removal process may include a wet etch process.

FIG. 5 shows the memory device after subsequent processing steps in which a switching layer 38 may be conformally deposited over top surface 36t of the top electrode 36, the side surfaces 40s of the electrode stack 40 and over the top surface of interlayer dielectric material 10 adjacent to the electrode stack 40. As previously described, the conformally deposited switching layer 38 conforms to or follows the contours of the electrode stack 40. For example, the switching layer 38 is in direct contact with the side surfaces 26s, 32s and 36s of the bottom electrode 26, middle electrode 32 and top electrode 36 respectively, and also in direct contact with the side surfaces 28s and 34s of the hard masks 28 and 34 respectively. The switching layer 38 may additionally be formed to have a horizontal portion 38H extending over the top surface of interlayer dielectric material 10, the horizontal portion 38H having a substantially planar top surface 38t. Suitable conformal deposition methods may include but not limited to atomic layer deposition (ALD) and chemical vapor deposition (CVD).

FIGS. 6A and 6B depict the memory device after subsequent processing steps in which a portion of the top electrode 36 is removed. The process may include lithography and etching processes to define the desired shape and dimensions of the top electrode. In an embodiment, the process for partial removal of the top electrode 36 may include removing a portion of the hard mask 34 to expose a portion of the top surface 32t of the middle electrode 32. For example, a patterning hard mask layer (not shown) may be formed over the switching layer 38 to shield a portion of the switching layer 38 and the electrode stack 40, and an etching process may then be performed to form the memory device having the cross-section depicted in FIG. 6B. In an example, the etching process may be an anisotropic etching process which may preferentially remove more unshielded materials from the switching layer 38, top electrode 36 and the hard mask 34 in the vertically downward direction compared to the lateral direction. The anisotropic etching process may also be designed to stop at a top surface 32t of the middle electrode 32. The patterning hard mask layer may then be removed with a suitable process. In an alternative process (not shown), the anisotropic etching process may be designed to stop at the top surface of the hard mask 34. An additional via etch through hard mask 34 to the top surface 32t may then be performed to form a via contact to the middle electrode 32. Subsequently, the process may continue with the formation of interconnect structures such as vias 22 and 24 and bit lines 16 and 18, and deposition of interlayer dielectric material 50 to form the memory device 100 in FIG. 1A or FIG. 2.

Referring to FIG. 7A in which like reference numerals refer to like features in FIG. 3A and which shows an exemplary cross-sectional view of memory device 200 along line X-X′ in accordance with an alternative embodiment. Memory device 200 may include features similar to memory device 100 but may include a modified electrode stack 40 with electrodes having different widths from the hard masks. In an exemplary embodiment, the hard masks may be recessed by performing a wet etch process designed to preferentially remove hard mask material in the lateral direction from the electrode stack 40. The top electrode 36 may have a width W_TEthat is longer than the width W_HM2of the hard mask 34 directly underneath the top electrode 36. The width W_HM2of the hard mask 34 may also be shorter than the width W_MEof the middle electrode 32. The top surface 34t of the hard mask 34 may be smaller than the bottom surface 36b of the top electrode 36 and the bottom surface of the hard mask 34 may be smaller than the top surface 32t of the middle electrode 32. The shorter width of the hard mask 34 results in a peripheral portion of the top electrode 36 overhanging the hard mask 34 on one or more sides, and a peripheral portion of the top surface 32t of the middle electrode 32 being uncovered by the hard mask 34. For example, the side surface 34s of the hard mask 34 may be recessed from the side surface 36s of the top electrode 36 on one or more sides of the hard mask 34 by a width y1. A bottom edge or corner 36eb of the top electrode 36 may be spaced from the side surface 34s of the hard mask 34 by width y1 and be in contact with the switching layer 38. A top edge or corner 32et of the middle electrode may also be spaced from the side surface 34s of the hard mask 34 and be in contact with the switching layer 38. Still referring to FIG. 7A, the middle electrode 32 may have a width W_MEthat is longer than the width W_HM1of the hard mask 28 between the middle electrode 32 and the bottom electrode 26. The width W_HM1of the hard mask 28 may also be shorter than the width W_BEof the bottom electrode 26. The shorter width of the hard mask 28 similarly results in a peripheral portion of the middle electrode 32 overhanging the hard mask 28 on one or more sides, and a peripheral portion of the top surface 26t of the bottom electrode 26 being uncovered by the hard mask 28. For example, the side surface 28s of the hard mask 28 may be recessed from the side surface 32s of the middle electrode 32 on one or more sides of the hard mask 28 by a width y2. A bottom edge or corner 32eb of the middle electrode 32 may be spaced from the side surface 28s of the hard mask 28 by width y2 and be in contact with the switching layer 38. A top edge or corner 26et of the bottom electrode 26 may also be spaced from the side surface 28s of the hard mask 28 and be in contact with the switching layer 38. The widths y1 and y2 may each be in the range of 2 nm to 3 nm. In some embodiments, width y1 may be substantially the same as width y2. In other exemplary embodiments, the top electrode width W_TEmay be substantially the same as the middle electrode width W_ME. In another embodiment, the middle electrode width W_MEmay be substantially the same as the bottom electrode width W_BE. In yet another embodiment, the widths of the top, middle and bottom electrodes are substantially the same, taking into consideration manufacturing allowances due to process variations.

Now referring to FIG. 7B, in which like reference numerals refer to like features in FIG. 3B and which shows an exemplary cross-sectional view of memory device 200 along line Y-Y′ in accordance with an alternative embodiment. The length L_TEof the top electrode 36 may be longer than the length L_HM2of the hard mask 34 directly underneath the top electrode 36. The middle electrode 32 may have a length L_MEthat is longer than the length L_HM1of the hard mask 28 between the middle electrode 32 and the bottom electrode 26. The length L_BEof the bottom electrode 26 may also be longer than the length L_HM1of the hard mask 28. In some embodiments, the length L_MEof the middle electrode 32 is substantially the same as the length L_BEof the bottom electrode 26, taking into consideration manufacturing allowances due to process variations. As an example and with reference to FIG. 7B, the side surface 34s′ of the hard mask 34 may be recessed from one of the side surface 36s′ of the top electrode 36 by a width y3 on one side of the electrode stack, while the side surface 36s′ of the top electrode 36 and side surface 34s′ of the hard mask 34, are substantially coplanar on an opposite side of the electrode stack. A bottom edge or corner 36eb of the top electrode 36 may be spaced from the side surface 34s′ of the hard mask 34 by width y3 and be in contact with the switching layer 38. In some embodiments, width y3 may be substantially the same as width y1. The side surface 28s′ of the hard mask 28 may be recessed from the side surface 32s′ of the middle electrode 32 on one or more sides of the hard mask 28 by a width y4. A bottom edge or corner 32eb of the middle electrode 32 may be spaced from the side surface 28s′ of the hard mask 28 by width y4 and be in contact with the switching layer 38. A top edge or corner 26et of the bottom electrode 26 may also be spaced from the side surface 28s′ of the hard mask 28 and be in contact with the switching layer 38. The widths y3 and y4 may each be in the range of 2 nm to 3 nm. In some embodiments, width y3 may be substantially the same as width y4. In other embodiments, widths y1, y2, y3 and y4 are substantially the same, for example, when the etching rate is uniform on all sides, while taking into consideration manufacturing allowances due to process variations.

In use, voltages may be applied to each of the top, middle and bottom electrodes through the conductive lines, in order to read, write or erase the memory device. Referring back to FIG. 3A, in accordance with an aspect of the exemplary embodiment, the bottom electrode 26 and top electrodes may act as active electrodes, and the middle electrode may act as an inert electrode. The memory device 100 may be programmed upon application of selected voltages to the relevant electrodes as desired. First referring to the unit cell 100A comprising the bottom electrode 26, the middle electrode 32 and the switching layer 38 extending between the two electrodes, applying a selected voltage to at least one of the electrodes creates a potential difference across the two electrodes. For example, the voltage applied may be a “SET” voltage, or VSET. One or more conductive filaments may be formed in at least a portion of the switching layer 38 extending between the bottom electrode 26 and middle electrode 32, thereby putting the unit cell 100A into a low resistance state (LRS). When a reverse voltage is applied, for example, a “RESET” voltage or VRESET, such that the conductive filaments can no longer be maintained between the two electrodes and thereby rupturing the conductive path therebetween, the memory device may then be placed into a high resistance state (HRS). In this way, the unit cell 100A can be written, erased or read. Next referring to the unit cell 100B which comprises the top electrode 36, the middle electrode 32 and the switching layer 38 extending between the two electrodes, unit cell 100B may be separately programmed from unit cell 100A by applying selected voltages to the top electrode 36 while the middle electrode 32 is being kept at the same potential for the programming of unit cell 100A. The operation of unit cell 100B with reference to the formation and destruction of filaments is similar to 100A and need not be further elaborated. Confinement of the conductive filaments to a specific region of the switching layer 38 by intentional design, for example, facilitating the formation of filaments at the edge or corners of the electrodes, allows for faster switching behavior between high resistance state (HRS) and low resistance state (LRS), leading to faster reading, writing, and erasing speeds of the memory device, as opposed to conductive filaments forming randomly within the switching layer in an unpredictable manner.

With reference to FIG. 8 in which like reference numerals refer to like features in FIG. 3A, an exemplary cross-section view of memory device 300 in accordance with an alternative embodiment is provided. Memory device 300 may include features similar to memory device 100 which have already been described and need not be repeated here. Compared to memory device 100, memory device 300 includes a top electrode 46 comprising a material different from the bottom electrode 26 and also different from the middle electrode 32. Top electrode 46 has a top surface 46t which may be covered by and in contact with the switching layer 38. The use of different electrode materials for each of the unit cells may enable better control of cell operations by having different potential values associated with a selected resistance state, for example, a low resistance state in unit cell 100A may correspond to a potential value that is different from the potential value corresponding to the low resistance state in unit cell 100B. Further, for certain electrode materials, additional resistance states may also be enabled by careful study and adjustment of the applied potential values associated with various resistance states. For example, for a single memory cell, a first applied potential value may be associated with a first high resistance state, whereas a second and different applied potential value may be associated with a second high resistance state different from the first high resistance state, providing two different high resistance states associated with two different applied potential values for a single memory cell. For a memory cell comprising two or more unit cells wherein the electrode materials are different, additional multiple resistance states may thus be possible, and may provide better control over cell operations due to the different associated applied potential values.

Now referring to FIG. 9 in which like reference numerals refer to like features in FIG. 3A, an exemplary cross-section view of memory device 400 in accordance with an alternative embodiment is provided. Memory device 400 may include features similar to memory device 100 which have already been described and will not be repeated here. Compared to memory device 100, hard masks 28 and 34 may have different thicknesses. For example, the thickness of hard mask 28, T_HM28, may be thinner than the thickness of hard mask 34, T_HM34. In another example, the thickness of hard mask 28, T_HM28, may be thicker than the thickness of hard mask 34, T_HM34. The difference in hard mask thicknesses results in a difference in the dimensions of the spacing between the top electrode 36 and the middle electrode 32, and the dimensions of the spacing between the middle electrode 32 and the bottom electrode 26. The dimensions of the spacing between electrodes is correlated to the magnitude of the switching voltage of the memory unit cell. For example, a shorter spacing between the electrodes may be associated with a switching voltage having a smaller magnitude than the switching voltage for electrodes separated by a larger spacing. Memory device 400 may be designed to have optimally low switching voltages for both unit cells 100A and 100B by adjusting the thickness of the hard mask materials 28 and 34. This may beneficially allow for improved power or energy savings during operation of the memory cell.

Referring to FIG. 10 which shows a schematic diagram of a memory array comprising a plurality of memory devices 100 which may be arranged in rows and columns and connected to bit lines that may be arranged substantially perpendicular to word lines and source lines, according to an aspect of the exemplary embodiment. The switching layer 38 has been omitted from the diagram but is understood to be part of the memory device 100. One of the memory devices in the array, memory device 100₁may be coupled to the source line SLn via the transistor T₁at the bottom electrode 26. The transistor T₁may be coupled to the word line, WLn at the transistor gate terminal, such that application of a selected voltage to the word line switches the transistor “on” or “off” to control the current flow through the transistor to the bottom electrode 26. The top electrode 36 may be connected to a first bit line, BLn, while the middle electrode may be connected to a second bit line, BL′n. A second memory device 100₂may similarly have the bottom electrode 26 coupled to the source line, SLn, and the word line, WLn, through another transistor T₂, and also have the top electrode 36 connected to a third bit line, BLn+1, and the middle electrode connected to a fourth bit line, BL′n+1. Additional memory devices 100₃, 100₄, up to memory device 100_nmay be connected in the array in a similar manner.

Table 1 below shows a set of electrical signals that may be applied to the aforementioned memory array for various operational states of selected memory cells, in accordance with an exemplary embodiment. For example, starting from pristine state where the memory device is at “0” for both unit cells, to program a selected memory device 100₁to “SET” state for both of the unit cells 100A and 100B, a voltage “V_on” is applied to turn on the transistor T, allowing current to pass through the transistor. The source line SLn is grounded, or kept at “0” potential, and a voltage “V₁₁” is applied to top electrode 36 via the first bit line BLn. The middle electrode connected to the second bit line BL′n is kept at floating potential. The voltage “V₁₁” is at a value sufficiently large enough to form filaments across both unit cells 100A and 100B, so that both unit cells are “written” or switched to a low resistance state (LRS), as represented by the “(11)” in the operation table.