12a is set to release an electrical charge by biasing its memory gate 22 and selection gate 24 so that electrons travel away from the memory gate 22 and become removed from the gate dielectric layer 26.

FIGS. 2 to 8 are cross-sectional views illustrating a method of fabricating a flash memory in accordance with some embodiments.

In FIG. 2, a dielectric layer 68, a first conductive layer 70, and a second conductive layer 72 are formed on the substrate 16. The second conductive layer 72 forms the selection gate 24.

As will become evident with discussion below, the dielectric layer 68 is used to create the gate dielectric layers 26 for the first and second memory cells 12a, 12b; and the first conductive layer 70 is used to create the memory gates 22 for the first and second memory cells 12a, 12b.

The dielectric layer 68, the first conductive layer 70, and the second conductive layer 72 may be formed using various semiconductor processing techniques. For example, the dielectric layer 68, the first conductive layer 70, and the second conductive layer 72 may be formed using a sputtering process, a chemical vapor deposition process, or an ion metal plasma (IMP) process, and then patterned using masking and etching techniques. In one embodiment, as shown in FIG. 2, a portion of the dielectric layer 68 (e.g., a layer 78, which will be discussed in further detail below) is first formed on the substrate 16, and then the second conductive layer 72 is formed on the portion of the dielectric layer 68. Subsequently, the remaining portions of the dielectric layer 68 are formed, and then the first conductive layer 70 is formed on the dielectric layer 68. In another embodiment, the second conductive layer 72 is formed directly on the substrate 16. In this embodiment, the second conductive layer 72 is first formed on the substrate 16, and then the dielectric layer 68 is formed on the substrate 16 and over the second conductive layer 72. Subsequently, the first conductive layer 70 is formed on the dielectric layer 68.

As previously discussed with respect to FIG. 1, in one embodiment, the gate dielectric layer 26 is a multilayer dielectric that includes a first layer 48, a second layer 50, and a third layer 52. In this embodiment, the dielectric layer 68 includes a first layer 74, a second layer 76, and a third layer 78. The first layer 74, the second layer 76, and the third layer 78 are used to create the first layer 48, the second layer 50, and the third layer 52, respectively, of FIG. 1. It is noted that portions of the first layer 74, the second layer 76, and the third layer 78 are formed over and on an upper surface 79 of the second conductive layer 72 as a byproduct of fabricating the multiple layers of the gate dielectric layer 26. For example, as shown in FIG. 2, a stack of a first portion of the second layer 76, a portion of the third layer 78, and a second portion of the second layer 76 are formed on the upper surface 79 of the second conductive layer 72. As will be discussed in further detail with respect to FIG. 7, the portions of the dielectric layer 68 that are on the upper surface 79 of the second conductive layer 72 will be removed in a subsequent process.

As previously discussed with respect to FIG. 1, in one embodiment, the gate dielectric layer 26 is an oxide-nitride-oxide (ONO) layer. In this embodiment, the first layer 74 of the dielectric layer 68 is made of oxide, the second layer 76 of the dielectric layer 68 is made of nitride, and the third layer 78 of the dielectric layer 68 is made of oxide. It is noted that embodiments of the present disclosure are not limited to foregoing materials, i.e., the gate dielectric layer 26 can be made of other suitable materials as previously discussed.

In one embodiment, the first conductive layer 70, and the second conductive layer 72 are made of conductive material. For example, in one embodiment, the first conductive layer 70 and the second conductive layer 72 are made of a doped polysilicon, metal such as Hf, Zr, Ti, Ta, TiN, TaN, Co, Ru, Al, Cu, and/or W, combinations thereof, or multi-layers thereof. It is noted that embodiments of the present disclosure are not limited to foregoing materials, i.e., the first conductive layer 70 and the second conductive layer 72 can be made of other suitable materials.

In FIG. 3, portions of the dielectric layer 68 are removed to create the gate dielectric layer 26. In one embodiment, the portions of the dielectric layer 68 are removed subsequent to the dielectric layer 68, the first conductive layer 70, and the second conductive layer 72 being formed on the substrate 16 in FIG. 2.

The portions of the dielectric layer 68 are removed to partially expose sidewalls 80 of the first conductive layer 70 and sidewalls 82 of the second conductive layer 72. In addition, the upper surface 54 of the gate dielectric layer 26 is exposed and the cavities 56 are created, which were discussed with respect to FIG. 1.

The portions of the dielectric layer 68 may be removed using various semiconductor processing techniques. For example, the portions of the dielectric layer 68 may be removed using masking and etching techniques, such as a wet etch.

In FIG. 4, a protective layer 84 is formed on the upper surface 54 of the dielectric layer 68 and in the cavities 56. In one embodiment, the protective layer 84 is formed subsequent to the cavities 56 being formed in FIG. 3. As will become evident with the discussion below, the protective layer 84 is used to create the protective cap 28.

The protective layer 84 may be formed using various semiconductor processing techniques. For example, the protective layer 84 may be formed using a sputtering process, a chemical vapor deposition process, or an IMP process, and then patterned using masking and etching techniques.

In one embodiment, the protective layer 84 is made of a dielectric material. In one embodiment, the protective layer 84 is made of nitride. It is noted that embodiments of the present disclosure are not limited to a protective layer 84 formed of nitride, i.e., the protective layer 84 can be made of materials other than nitride. For example, the protective layer 84 may include silicon oxide; a high dielectric constant (high-K) dielectric material selected from one or more of hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HMO), hafnium titanium oxide (HMO), and hafnium zirconium oxide (HfZrO); combinations thereof; and/or other suitable materials.

In one embodiment, the protective layer 84 is made of the same material as the dielectric layer 68 or the same material of at least one of the materials making up dielectric layer 68 when dielectric layer 68 includes more than one material. For example, in one embodiment, the dielectric layer 68 is made of the same material as the second layer 76.

As the protective layer 84 covers the upper surface 54, the gate dielectric layer 26 is not left exposed during subsequent fabrication processes. As a result, conductive materials cannot be deposited onto the gate dielectric layer 26 and/or the gate dielectric layer 26 is protected from possible damage from subsequent fabrication processes, such as the processes that will be discussed with respect to FIGS. 5-8. Preventing deposition of conductive materials onto gate dielectric layer 26 and/or damage to the gate dielectric layer 26 ensures that the memory gate 22 and the selection gate 24 are electrically isolated from each other by the gate dielectric layer 26, and minimizes potential current leakage between the memory gate 22 and the selection gate 24.

In FIG. 5, portions of the first conductive layer 70 are removed to create the memory gates 22. In one embodiment, portions of the first conductive layer 70 are removed subsequent to the protective layer 84 being formed in FIG. 4.

The portions of the first conductive layer 70 are removed to partially expose outer surfaces 86 of the dielectric layer 68 and expose an inner surface 88 of the dielectric layer 68.

The portions of the first conductive layer 70 may be removed using various semiconductor processing techniques. For example, the portions of the first conductive layer 70 may be removed using masking and etching techniques.

In one embodiment, the portions of the first conductive layer 70 are removed in two separate steps. In a first step, portions of the first conductive layer 70 that are on the outer surfaces 86 of the dielectric layer 68 are removed to form the memory gates 22. In particular, a first hard mask (e.g., a silicon nitride layer) is formed on portions of the first conductive layer 70 that are on the inner surface 88 and portions of the first conductive layer 70 that form the memory gates 22. The remaining portions of the first conductive layer 70 are left uncovered by the first hard mask. The uncovered portions of the first conductive layer 70 are then removed using, for example, a wet etch. In a second step, the portions of the first conductive layer 70 that are on the inner surface 88 are removed. Namely, a second hard mask is formed on the portions of the first conductive layer 70 that form the memory gates 22 and on the first hard mask. The portions first conductive layer 70 that are on the inner surface 88 are left uncovered by the second hard mask. The portions first conductive layer 70 that are on the inner surface 88 are then removed using, for example, a wet etch. Subsequently, the first and second hard masks are removed to obtain the first conductive layer 70 as shown in FIG. 5. It is noted that photoresist coatings may also be used instead of the first hard mask and/or the second hard mask. In addition, the first and second steps may be reversed. For example, the portions of the first conductive layer 70 that are on the inner surface 88 may be removed first, and the portions of the first conductive layer 70 that are on the outer surfaces 86 of the dielectric layer 68 may be removed second.

In FIG. 6, portions of the dielectric layer 68 are removed to expose portions of an upper surface 89 of the substrate 16. In one embodiment, portions of the dielectric layer 68 are removed subsequent to the portions of the first conductive layer 70 being removed in FIG. 5.

Outer portions of the dielectric layer 68 are removed to expose outer portions 90a of the upper surface 89, and an inner portion of the dielectric layer 68 is removed to expose an inner portion 90b of the upper surface 89. As will be discussed with respect to FIG. 7, portions of the upper surface 89 are exposed to form source and drain regions.

It is noted that the portions of the dielectric layer 68 may be removed in multiple steps. For example, in one embodiment, the outer portions of the dielectric layer 68 are removed to expose the outer portions 90a of the upper surface 89, and the inner portion of the dielectric layer 68 is subsequently removed to expose the inner portion 90b of the upper surface 89. Conversely, in one embodiment, the inner portion of the dielectric layer 68 is removed to expose the inner portion 90b of the upper surface 89, and the outer portions of the dielectric layer 68 are subsequently removed to expose the outer portions 90a of the upper surface 89.

As previously discussed with respect to FIG. 1, in one embodiment, the drain region 20 is a common drain and is shared by both the first and second memory cells 12a, 12b. In order to form a drain region with a sufficient size to be shared by the first and second memory cells 12a, 12b, in one embodiment, portions of the protective layer 84 are also removed. For example, as shown in FIG. 6, portions of the dielectric layer 68 and the protective layer 84 are removed such that the exposed portion of the upper surface 89 between the selection gates 24 has a seventh dimension d7.

In one embodiment, the dimension d7 is between 400 and 500 angstroms. It is noted that the seventh dimension d7 is not limited to the foregoing and in other embodiments may be smaller or greater than the example given above. For example, the memory 10 may be scaled down such that the seventh dimension d7 is between 300 and 400 angstroms. Alternatively, the memory 10 may be scaled up such that the seventh dimension d7 is between 500 and 600 angstroms.

The portions of the dielectric layer 68 and/or the protective layer 84 may be removed using various semiconductor processing techniques. For example, the portions of the dielectric layer 68 and/or the protective layer 84 may be removed using masking and etching techniques.

In FIG. 7, the source regions 18 and the drain region 20 are formed in the substrate 16. In one embodiment, the source regions 18 and the drain region 20 are formed subsequent to the portions of the dielectric layer 68 being removed in FIG. 6.

The source regions 18 are formed in the outer portions 90a of the upper surface 89 of the substrate 16, and the drain region 20 is formed in the inner portion 90