FIG. 3A illustrates a cross-sectional view of a semiconductor device package 3A, in accordance with some embodiments of the present disclosure. The semiconductor device package 3A is similar to the semiconductor device package 2 as shown in FIG. 2A, and some of the differences therebetween are described below.

The dam structure 33s includes portions 32s1 and 32s2. The portion 32s1 and the portion 32s2 of the dam structure 33s are separated from each other. For example, there is a gap between the portion 32s1 and the portion 32s2 of the dam structure 33s. The dielectric layer 13d may extend within the gap between the portion 32s1 and the portion 32s2 of the dam structure 33s. In some embodiments, the dam structure 33s may include any number of portions separated from each other.

FIG. 3B illustrates a cross-sectional view of a semiconductor device package 3B, in accordance with some embodiments of the present disclosure. The semiconductor device package 3B is similar to the semiconductor device package 1 as shown in FIG. 1A, and some of the differences therebetween are described below.

As shown in FIG. 3B, the circuit layer 11 include multiple dielectric layers and conductive layers. An electronic component 34 is disposed on the surface 112 of the circuit layer 11 and electrically connected to the conductive layers of the circuit layer 11. The electronic component 11 can be electrically connected with the interconnection structure 13 and the circuit layer 15 through the circuit layer 11. The electronic component 11 may be a chip or a die including a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such resistors, capacitors, inductors, or a combination thereof.

Electrical contacts 36 (e.g., solder balls) are disposed on the surface 112 of the circuit layer 11. The electrical contacts 36 are electrically connected to the conductive layers of the circuit layer 11. The electrical contacts 36 can provide electrical connections between the semiconductor package device 3B and external components (e.g. external circuits or circuit boards). In some embodiments, the electrical contact 36 includes a controlled collapse chip connection (C4) bump, a ball grid array (BGA) or a land grid array (LGA).

The package body 35 is disposed on the surface 112 of the circuit layer 11. The package body 35 covers the electronic component 34. The package body 35 covers a portion of the electrical contacts 36 and exposes another portions of the electrical contacts 36. In some embodiments, the package body 35 includes an epoxy resin having fillers dispersed therein.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D and FIG. 4E illustrate cross-sectional views of a semiconductor manufacturing method, in accordance with some embodiments of the present disclosure. FIG. 4A′, FIG. 4B′, FIG. 4C′, FIG. 4D′ and FIG. 4E′ illustrate top views of the respective structures as illustrated in FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D and FIG. 4E, in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 4A, FIG. 4A′, FIG. 4B, FIG. 4B′, FIG. 4C, FIG. 4C′, FIG. 4D, FIG. 4D′, FIG. 4E and FIG. 4E′ can be used to manufacture the interconnection structure 13 as shown in FIG. 1A.

Referring to FIG. 4A and FIG. 4A′, a carrier 49 is provided. In some embodiments, the carrier 49 may include an adhesive layer 13h disposed thereon.

Referring to FIG. 4B and FIG. 4B′, one or more conductive structures 13p (e.g., conductive pillars/columns/pins/posts) are disposed on the adhesive layer 13h. In some embodiments, a lateral surface (or sidewall) of the conductive structures 13p are connected to the adhesive layer 13h. For example, the conductive structures 13p lie down on the adhesive layer 13h. In some embodiments, the conductive structures 13 are parallel to each other and spaced apart from each other.

Referring to FIG. 4C and FIG. 4C′, a dielectric layer 13d is formed on the adhesive layer 13h to cover the conductive structures 13p. In some embodiments, the dielectric layer 13d fully covers the conductive structures 13p. For example, the dielectric layer 13d covers both terminals of the conductive structures 13p. In some embodiments, the dielectric layer 13d may be formed by, for example, lamination, molding or any other suitable processes. Then, the carrier 49 is removed from the adhesive layer 13h (e.g., de-carrier) as shown in FIG. 4D and FIG. 4D′.

Referring to FIG. 4E and FIG. 4E′, singulation may be carried out to separate (or divide) the structure as shown in FIG. 4D and FIG. 4D′ into two parts. For example, the singulation may be carried out through the dielectric layer 13d and the conductive structures 13p. In each individual part, a portion of the conductive structures (e.g., a surface 13p2) is exposed from the dielectric layer 13d. In some embodiments, the singulation may be carried out by, for example, cutting or any other suitable processes.

FIG. 5A and FIG. 5B illustrate cross-sectional views of a semiconductor manufacturing method, in accordance with some embodiments of the present disclosure. FIG. 5A′ and FIG. 5B′ illustrate top views of the respective structures as illustrated in FIG. 5A and FIG. 5B, in accordance with some embodiments of the present disclosure. FIG. 5A″ and FIG. 5B″ illustrate top views of the respective structures as illustrated in FIG. 5A and FIG. 5B, in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 5A, FIG. 5A′, FIG. 5B and FIG. 5B′ can be used to manufacture the interconnection structure 23 as shown in FIG. 2A. In some embodiments, the method in FIG. 5A, FIG. 5A″, FIG. 5B and FIG. 5B″ can be used to manufacture the interconnection structure 33 as shown in FIG. 3A. In some embodiments, the operations as shown in FIG. 5A and FIG. 5B are similar to the operations as shown in FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D and FIG. 4E, and some of the differences therebetween are described below.

Referring to FIG. 5A and FIG. 5A′, prior to the placement of the conductive structures 13p on the adhesive layer 13h, a dam structure 23s is disposed on the adhesive layer 13h. Two adjacent dam structures 23s are spaced apart from each other to define a trench to accommodate the conductive structures 13p. The dam structure 23s can prevent the conductive structures 13p from rolling or moving during the manufacturing processes. In some embodiments, each dam structure 23s may include one piece as shown in FIG. 5A′. In other embodiments, as shown in FIG. 5A″, each dam structure 33s may include many pieces 33s1, 33s2 separated from each other.

Then, the operations same as or similar to the operations as shown in FIG. 4C, FIG. 4D and FIG. 4E (e.g., the formation of the dielectric layer 13d, de-carrier, singulation and the like) may be carried out to the structures as shown in FIG. 5A, 5A′ and FIG. 5A″ to form the structures as shown in FIG. 5B, 5B′ and FIG. 5B″.

FIG. 6A, FIG. 6B and FIG. 6C illustrate cross-sectional views of a semiconductor manufacturing method, in accordance with some embodiments of the present disclosure. FIG. 6A′, FIG. 6B′ and FIG. 6C′ illustrate top views of the respective structures as illustrated in FIG. 6A, FIG. 6B and FIG. 6C, in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 6A, FIG. 6A′, FIG. 6B, FIG. 6B′, FIG. 6C and FIG. 6C′ can be used to manufacture the interconnection structure 23 as shown in FIG. 2A. In some embodiments, the operations as shown in FIG. 6A, FIG. 6B and FIG. 6C are similar to the operations as shown in FIGS. 5A and 5B, and some of the differences therebetween are described below.

Referring to FIG. 6A and FIG. 6A′, a patterned dielectric layer 63 is provided. The patterned dielectric layer 63 includes one or more trenches 63t for accommodating the conductive structures 13p. The patterned dielectric layer 63 may function as the dam structure 23 as shown in FIG. 5A to prevent the conductive structures 13p from rolling or moving during the manufacturing processes.

Referring to FIG. 6B and FIG. 6B′, the patterned dielectric layer 63 is disposed on the adhesive layer 13h. In some embodiments, the patterned dielectric layer 63 may be connected to the adhesive layer 13h by, for example, lamination or other suitable processes.

Referring to FIG. 6C and FIG. 6C′, the conductive structures 13p are disposed within the respective trenches 63t defined by the patterned dielectric layer 63. Then, the operations same as or similar to the operations as shown in FIG. 4C, FIG. 4D and FIG. 4E (e.g., the formation of the dielectric layer 13d, de-carrier, singulation and the like) may be carried out to the structures as shown in FIG. 6C and FIG. 6C′ to form the structure as shown in FIG. 5B and FIG. 5B′.

FIG. 7A, FIG. 7B, FIG. 7C and FIG. 7D illustrate cross-sectional views of a semiconductor manufacturing method, in accordance with some embodiments of the present disclosure.

Referring to FIG. 7A, a carrier 79 is provided. In some embodiments, the carrier 79 may include an adhesive layer 79h disposed thereon. A patterned dielectric layer 73 is disposed on the adhesive layer 79h. The patterned dielectric layer 73 includes one or more openings 73h to expose the adhesive layer 79h.

Referring to FIG. 7B, the conductive structures 13p are disposed with the respective openings 73h. For example, one of the terminals (e.g., a bottom surface) of each conductive structures 13p is connected to the adhesive layer 79h exposed from the patterned dielectric layer 73. For example, a lateral surface is surrounded by the patterned dielectric layer 73. In some embodiments, there is a gap between the lateral surface of the conductive structures 13p and the patterned dielectric layer 73. For example, a diameter (or width) of the openings 73h is larger than a diameter (or width) of the conductive structures 13p. In other embodiments, the diameter (or width) of the openings 73h may be equal to the diameter (or width) of the conductive structures 13p.

Referring to FIG. 7C, a dielectric layer 74 is formed on the adhesive layer 79h to cover the conductive structures 13p and the dielectric layer 73. In some embodiments, the dielectric layer 74 may further extend within the gap between the conductive structures 13h and the dielectric layer 73. In some embodiments, the dielectric layer 74 may be formed by, for example, lamination, molding or any other suitable processes.

Referring to FIG. 7D, the carrier 79 and the adhesive layer 79h are then removed to expose the surface 13p1 of the conductive structures 13p.

FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, FIG. 8E and FIG. 8F illustrate cross-sectional views of a semiconductor manufacturing method, in accordance with some embodiments of the present disclosure. FIG. 8A′, FIG. 8B′, FIG. 8C′ and FIG. 8D′ illustrate top views of the respective structures as illustrated in FIG. 8A, FIG. 8B, FIG. 8C and FIG. 8D, in accordance with some embodiments of the present disclosure. In some embodiments, the method in FIG. 8A, FIG. 8A′, FIG. 8B, FIG. 8B′, FIG. 8C, FIG. 8C′, FIG. 8D, FIG. 8D′, FIG. 8E and FIG. 8F can be used to manufacture the semiconductor device package device 1 as shown in FIG. 1A.

Referring to FIG. 8A and FIG. 8A′, a carrier 10 is provided. In some embodiments, the carrier 10 may be or include a glass carrier. A circuit layer 11 including a conductive layer 11c and a dielectric layer 11d is formed on the carrier 10. The dielectric layer 11d may define one or more recesses 11r to expose a portion of the conductive layer 11c.

Referring to FIG. 8B and FIG. 8B′, electrical contacts (e.g., solder balls) 12 are formed within the recesses 11r and electrical connected to the conductive layer 11c exposed from the dielectric layer 11d. In some embodiments, there is a gap between the electrical contacts 12 and the sidewall of the recesses 11r. In some embodiments, the electrical contacts 12 may be formed by, for example, printing or any other suitable processes.

Referring to FIG. 8C and FIG. 8C′, the interconnection structure as shown in FIG. 4E and FIG. 4E′ is disposed on the circuit layer 11. The surface 13p2 of the conductive structures 13p exposed from the dielectric layer 13d is connected to the electrical contacts 12. In some embodiments, as shown in FIG. 8C′, there may be a plurality of interconnection structures as shown in FIG. 4E and FIG. 4E′ disposed on the circuit layer 11 and separated from each other depending on different design requirements.

For example, the interconnection structure as shown in FIG. 8C′ may include an interconnection structure 13pf located at or adjacent to the center of the dielectric layer 11d. The interconnection structure 13pf may function as a feeding point of the antenna. The interconnection structures including the conductive structures 13p surround the interconnection structure 13pf. In some embodiments, the conductive structures 13p may be connected to ground.

In other embodiments, the interconnection structure as shown in FIG. 8C and FIG. 8C′ can be replaced by the interconnection structure as shown in FIG. 5B, FIG. 5B′, FIG. 5B″ or FIG. 7D.

Referring to FIG. 8D and FIG. 8D′, a package body 14 is formed on the circuit layer 11 to cover the interconnection structures and the electrical contacts 12. In some embodiments, the package body 19 may fully cover the interconnection structures and the electrical contacts 12. In some embodiments, the package body 19 may further extend within the gap between the electrical contacts 12 and the sidewall of the recesses 11r. For example, the package body 19 may be in contact with a portion of a top surface of the conductive layer 11c. In some embodiments, the package body 14 is formed by, for example, by a transfer molding technique, a compression technique or any other suitable techniques.

Referring to FIG. 8E, a portion of the package body 14 and the dielectric layer 13d is removed to expose the surface 13p1 of the conductive structures 13p to form the interconnection structure 13. In some embodiments, a portion of the conductive structures 13p may be removed as well. In some embodiments, the package body