110 all 2-norms satisfy the pruning criteria (e.g., all 2-norm values are below a threshold value) and as a result of even a single filter failing to satisfy the pruning criteria, the i-th filter of all 18 layers cannot be removed. However, in an embodiment, if all 2-norms satisfy the pruning criteria the grouped filter from all layers can be simultaneously removed.

In an embodiment, VACL regularization penalizes variance within a group (e.g., variance of the i-th filter between layers) to encourage each group to not only have small group lasso cost, but also reduces the variance of weights within a group and in turn efficiently align the sparsity of all connected layers. In an embodiment, for a group comprising the i-th filter of two or more convolutional layers, group lasso cost is minimized or reduced and variance of weights within the group is also reduced to reduce overall weights within the group to zero or substantially near zero, allowing the i-th filter of each layer to be simultaneously removed 112. It should be noted that simultaneous removal refers to the atomic nature of the removal of the multiple filters as being an all-or-nothing operation (e.g., removal of some but not all of the filters in a group is disallowed) and not necessarily that the filters are temporally removed at the same time.

In an embodiment, the neural network illustrated in FIG. 1 is implemented based on or using a ResNet architecture. In an embodiment, the neural network is trained to solve one or more problems in computer vision including but not limited to: object detection; image classification; feature detection; and more. In an embodiment, a neural network is trained on an image collection to perform a computer vision related task (e.g., boundary detection) and a trained model is produced from the training process with a set of weights, filters, and layers to generate predictions at inference time. In an embodiment, the trained neural network is pruned to reduce the computational complexity of the neural network by re-organizing weights, filters, layers, etc. to reduce the computational complexity of running the neural network at inference time. In an embodiment, the neural network is pruned to remove one or more filters or layers from the neural network using VACL regularization to produce a pruned neural network without substantially affecting the accuracy of the (un-pruned) trained neural network. In an embodiment, accuracy or quality of the neural network not being substantially affected is determined by testing the accuracy of an un-pruned neural network against a training data set to determine a baseline accuracy or quality metric and then running pruned neural network on the same training data set to determine the accuracy or quality metrics for the pruned neural network; the observed metrics are compared, and if the accuracy of the pruned neural network is inferior to that of the original network or has decrease in metrics that exceeds a threshold value, then the pruning may be said to have substantially affected the quality of the neural network and, in an embodiment, the pruned neural network is rejected and another re-organization of the weights is to be attempted.

In an embodiment, VACL is defined as an extension of Group Lasso which constrains the variance of weights in a weight group in addition to constraining the 2-norm of the layer groups. In an embodiment, VACL efficiently enforces aligned structured sparsity in one layer group L. In an embodiment, a model has multiple layer groups and G denotes the set of all layer groups in a model where L_gdenotes the g-th layer group. In an embodiment, VACL regularization is defined as:

R
VACL

=

∑

g
∈
G

∑

i
=
1

M

p
i
g

[

r

2
⁢
norm

+

r
var

]

⁢

with
⁢

r

2
⁢
norm

=



W
i
g



2

⁢

and
⁢

r
var

=



(

❘
"[LeftBracketingBar]"

W
i
g

❘
"[RightBracketingBar]"

-

❘
"[LeftBracketingBar]"

W
i
g

_

❘
"[RightBracketingBar]"

·
1

)



2

.

In an embodiment, the weights of the i-th filter in layer group L_gare denoted as

W
i
g

,

the first term in the inner summand is the 2-norm of

W
i
g

,

the second term is the 2-norm of weights absolute difference

❘
"[LeftBracketingBar]"

W
i
g

❘
"[RightBracketingBar]"

-

❘
"[LeftBracketingBar]"

W
i
g

_

❘
"[RightBracketingBar]"

·
1

where

❘
"[LeftBracketingBar]"

W
i
g

_

❘
"[RightBracketingBar]"

is the mean of

❘
"[LeftBracketingBar]"

W
i
g

❘
"[RightBracketingBar]"

,

and 1 is a vector filled with ones. In an embodiment, it sums results over all M filters to obtain the regularization loss for the layer group L_gand sums up over all layer groups in G. In an embodiment, r_2normis the 2-norm inherited from Group Lasso and the term r_varis a constraint to reduce the variance of the absolute values of the weights in W_i. In an embodiment, the contours of VACL are in accordance with those discussed in connection with FIG. 3, having contours with four sharp corners in two diagonal directions to constrain the weights' absolute values.

In an embodiment, the total loss of the model is described as:

ℒ
⁡
(

X
,
W

)

=

∑

n
=
1

N

E
[

y
n

,

ℱ
⁡
(

x
n

,
W

)

]

+

λ
1

⁢

R
VACL

(

W
g

)

+

λ
2

⁢

R
GL

(

W
s

)

with R^VACLthe VACL constraint applied to all layer groups, and R^GLthe Group Lasso applied to other layers that are not connected by element-wise operators (e.g., element-wise addition), λ₁and λ₂are regularization weights for R^VACLand R^GLrespectively, W_gdenotes the weights in the layer groups, and W_sdenotes the weights in other layers. In an embodiment, the four convolutional layers bolded in FIG. 1 are constrained by R^VACLand the three convolutional layers not in bold are constrained by R^GLby defining one filter as a weight group.

In an embodiment, FIG. 2 illustrates a system 200 in which various embodiments are implemented in accordance with one embodiment. In an embodiment, FIG. 2 illustrates a portion of a neural network 202 and two different aligned sparsities. In an embodiment, FIG. 2 illustrates a portion of a neural network 202. In an embodiment, FIG. 2 depicts an example residual block in accordance with one or more versions of ResNet (e.g., ResNet 110). In an embodiment, a traditional network has each layer feed into the next layer, whereas in a network, a layer feeds into the next layer and also directly into later layers (e.g., multiple hops away). In an embodiment, skip-connections—also referred to as residual connections—are used to skip training of intermediate hidden layers. In an embodiment, the skip connections are used so that during training, the neural network can either train the layer in residual blocks or skip the training for those layers using skip connections. In an embodiment, the skip connections are used to solve problems related to vanishing gradients.

In an embodiment, FIG. 2 illustrates a neural network with two common layers, in bold (e.g., CONV 1 and CONV 3), in which the removal of a filter in one layer necessitates the removal of a corresponding filter in another layer. In an embodiment, for layers that are related to each other through element-wise operation, the i-th filter of the layers are grouped together and either kept or removed simultaneously during pruning. In an embodiment, the output shape of the layers in a group are to have the same dimensions.

FIG. 2 illustrates, in an embodiment, a first architecture 204 having different structured sparsity. In an embodiment, this can arise when sparsity constraints are applied to layers individually. In an embodiment, although each layer has only two effective filters to be remained, overall there are four filters which cannot be removed. In an embodiment, FIG. 2 illustrates a second architecture 206 in which two layers have aligned sparsity cross filters, and only two filters will be remained. In an embodiment, all connected layers that are to have the same indices of filters to be removable.

In an embodiment, FIG. 3 illustrates a diagram 300 illustrating regularization loss contours among L1, group lasso, and VACL, in accordance with one embodiment. In an embodiment, the L1 regularization 302 encourages individual weights close to the four poles. In an embodiment, the group lass regularization 304 with x and y in the same group, the plot has smooth circle edges in expansion of the x-y plane, which is generated by the 2-norm of x and y. In an embodiment, the group lasso has W=(w₁, w₂) in the same group. In an embodiment, the VACL regularization 306 is illustrated with x and y in the same group and with W=(w₁, w₂) the same group and u the mean of |w₁| and |w₂|. In an embodiment, VACL regularization has an item that regularizes weight variances within each group and, as a result, the VACL contour has non-smooth edges composed of curves and four sharp angles. Each angle, in an embodiment, represents a direction in which the absolute value of x is equal to the absolute value of y, which means encouraging |x| and |y| to be equal. In an embodiment, VACL regularization is able to consistently remove filters from grouped layers across multiple runs, whereas L1 and cross layer group lasso (CLGL) either fail or cannot guarantee the filter removal for each run. In an embodiment, 2-norm of a weight filter is used as the criteria to determine whether a filter is to be removed or retained in the network. In an embodiment, a filter is removable if its 2-norm is below a threshold. In an embodiment, a filter connected by skip-connections is removable if and only if: (1) its 2-norm is below a threshold value (e.g., predetermined threshold); and (2) the 2-norm of all of the same indexed filters in multiple connected layers are below the threshold value simultaneously.

In an embodiment, a voting system is used to determine whether or not the i-th filter of every connected layer can be removed. In an embodiment, vote=1 denotes that the 2-norm of a filter is above the threshold in a certain layer. In an embodiment, votes for the i-th filter across all layers connected by element-wise operations (e.g., adding operations) are counted and if the count vote equals to exactly 0, then the i-th filter for all of those layers are removed. In an embodiment, if the vote count is not zero, then it is implied that the 2-norm of all of the same indexed filters in multiple connected layers are not below the threshold value simultaneously and therefore that the i-th filter cannot be removed. In an embodiment, the vote count is normalized by the total number of connected layers and is used to determine a vote percentage. In an embodiment, a vote percentage equal to 1 means that none of the i-th filter across the grouped layers fulfills the requirement; vote percentage=0.5 means half of the i-th filter fulfills requirement 1, so that requirement (2) from the preceding paragraph is not fulfilled; vote percentage=0 means all of the i-th filter fulfills requirement 1, so that requirement (2) of the preceding paragraph is also fulfilled.

In an embodiment, FIG. 4 illustrates a system 400 illustrating an iterative training and pruning pipeline, in accordance with one embodiment. In an embodiment, an iterative includes a training stage and a pruning stage and incorporates two hybrid regularization schemes: the first scheme 402 applies L1 and VACL alternatively across training stages (e.g., a first stage applies L1 and the next stage applies VACL, and so on), and the second scheme 404 applies VACL and LIS alternatively across training stages where LIS means applying L1 regularization to layers that are not connected by skip-connections. The training-pruning strategy improves pruning efficiency and demonstrates the generality of VACL regularization methods.

In an embodiment, the first scheme 402 illustrates a pipeline algorithm that applies L1 regularization to all weights across all layers in a model (e.g., residual network) and then prunes the model. In an embodiment, after pruning, layers that are not connected by skip-connections are successfully pruned but layers connected by skip-connections are hardly pruned. In an embodiment, VACL regularization is then applied to the regularize filters in the connected layers and those layers are pruned. In an embodiment, this alternating regularization iterates until the model size and model accuracy are well balanced.

In an embodiment, the second scheme 404 illustrates a pipeline algorithm that first applies VACL to regularize weights in the connected layers, denoted as group layers, and prunes the network. In an embodiment, LIS regularization is applied on single layers and pruned. In an embodiment, single layers refer to layers that are not connected by skip-connections.

FIG. 5 shows an illustrative example of a process 500 to use weight information corresponding to a neural network, wherein weight information of at least a first one or more layers of the neural network is modified to compensate for deactivating one or more second layers of the neural network, in accordance with an embodiment. In an embodiment, some or all of the process 500 (or any other processes described herein, or variations and/or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and may be implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. The code, in an embodiment, is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. The computer-readable storage medium, in an embodiment, is a non-transitory computer-readable medium. In an embodiment, at least some of the computer-readable instructions usable to perform the process 500 are not stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). A non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals. In an embodiment, the process 500 to use weight information corresponding to a neural network, wherein weight information of at least a first one or more layers of the neural network is modified to compensate for deactivating one or more second layers of the neural network is implemented or executed using or based on any suitable combination of computer circuitry, including but not limited to processors, arithmetic logic units (ALUs), integrated circuitry (e.g., application-specific integrated circuit), memory units, etc., in accordance with FIGS. 6-10, as described in greater detail herein above and below.

In an embodiment, the process includes grouping 502 filters across two or more layers of a neural network. In an embodiment, the neural network is a trained neural network where the weights of the neural network have, prior to the pruning process, been configured so that inputs to the neural network are used to generate outputs or predictions. In an embodiment, the neural network is a residual network such as a ResNet-based network. In an embodiment, the neural network includes ResNet blocks with convolutional layers connected by element-wise operations which are grouped by taking the i-th filter of each of the connected layers. In an embodiment, the system iterates through each of the filters (e.g., 1^st, 2^nd, 3^rd. . . N^thof N filters) to prune the network and reduce how many parameters are in the network and improve test time performance. In an embodiment, grouping filters across two or more layers comprises determining that a first filter of a first layer and a second filter of a second layer (e.g., the i-th filter of both layers) are to be removed together (e.g., because the first filter and the second filter are connected by a skip-connection).

In an embodiment, the process includes performing 504 a regularization on the group to enforce aligned structure sparsity. In an embodiment,

R
vacl

=

∑

g
∈
G

R
g
vacl

defines a VACL regularization where the first term of the VACL regularization calculates 2-norm of w_k^g, and the second term of the VACL regularization calculates the 2-norm of weights absolute difference of w_k^gwhere the weights of the k^thfilter in layer group g are denoted as

w

k
g

.

In an embodiment, the total cost of the model, as shown in the loss function [Image Omitted] (X, W) described above is extended as:

ℒ
⁡
(

X
,
W

)

=

∑

n
=
1

N

E
[

y
n

,

ℱ
⁡
(

x
n

,
W

)

]

+

λ
⁢

R
vacl

⁢

=

∑

n
=
1

N

E
[

y
n

,

ℱ
⁡
(

x
n

,
W

)

]

⁢

+

λ
(

∑

g
∈
G

{

∑

k
=
1

K

p
k
g

[



w
k
g



2

+



(

❘
"[LeftBracketingBar]"

w
k
g

❘
"[RightBracketingBar]"

-

❘
"[LeftBracketingBar]"

w
k
g

_

❘
"[RightBracketingBar]"

)



2

]

}

)

In an embodiment, VACL regularization has an item that regularizes weight variance inside each group and is in accordance with techniques described elsewhere in this disclosure, including but not limited to those discussed in connection with FIG. 1.

In an embodiment, the process includes determining whether 506 the filter group is removable. In an embodiment, the system determines whether the filters are removable based on whether the result of the regularization satisfies a pruning criteria. In an embodiment, a filter in a layer connected by skip-connection with other layers is removable if and only if: (1) its 2-norm is below a threshold value (e.g., predetermined threshold); and (2) the 2-norm of all of the same indexed filters in multiple connected layers are below the threshold value simultaneously. If the system determines that the filter group is removable, the process includes simultaneously removing 508 the filters from all of the layers of the group, in accordance with one embodiment. In an embodiment, simultaneous removal refers to the atomic nature of the removal of the multiple filters as being an all-or-nothing operation (e.g., removal of some but not all of the filters in a group is disallowed) and not necessarily that the filters are concurrently removed at the same time. If the system determines that the filter group cannot be removed, the system keeps 510 the filters and, in an embodiment, continues to iterate through all of the filters to determine whether a different group of filters (e.g., for the i+l-th index) can be pruned.

FIG. 6A illustrates layer groups implemented according to different deep neural networks 600, 602, and 604, in accordance with one embodiment. In an embodiment, FIG. 6A illustrates respective portions of different neural network architectures connected by skip-connections. In an embodiment, most convolutional layers illustrated in FIG. 6A are located on the respective residual paths shown, except for a projection shortcut. In an embodiment, all layers within a network that are bolded have the same output shape D_h×D_w×M, where D_h×D_wis the size of the feature maps and M is the number of feature maps. In an embodiment, these layers are element-wise connected and for a layer group denoted by L. It should be noted that the neural networks illustrated in FIG. 6A, in an embodiment, are implemented separately and without a loss of generality, that the dimension of the bolded layers in one neural network (e.g., numeral 600) and another neural network (e.g., numeral 602) do not necessarily have the same dimensions. In an embodiment, numeral 600 illustrates a neural network according to one or more variations of ResNeXt. In an embodiment, numeral 602 illustrates a neural network according to one or more variations of Xception. In an embodiment, numeral 604 illustrates a neural network according to one or more variations of ResNet. In an embodiment, for a convolutional layer that generates M output feature maps, there are M filters, each having C×K×K weighs, where C is the number of input feature maps, and K×K is the filter size.

In an embodiment, FIG. 6B illustrates three layer groups in a neural network (e.g., according to ResNet 110 or variations thereof) for CIFAR10. In an embodiment, the bolded blocks in a first block 606 form a first layer group L1, the bolded blocks in the second block 608 form a second layer group L2, and the bolded blocks in the third block 610 form a third layer group L2. In an embodiment, the feature maps generated by weights from the same indexed filter are aggregated to one output feature map. In an embodiment, when a feature map is redundant, filters used to generate it can be removed—based on the idea of Group Lasso regularization, a weight group W_ican be defined as: W_i=∪W_liwith i∈[1, M], l the index of a layer in L, and w_lithe weights of filter i in layer l. In an embodiment, by defining such weight groups, structural sparsity constraints such as Group Lasso can be applied to enforce group level sparsity so that the i-th filters of all layers in L are either significant or redundant.

FIG. 7 illustrates a parallel processing unit (“PPU”) 700, in accordance with one embodiment. In an embodiment, the PPU 700 is configured with machine-readable code that, if executed by the PPU, causes the PPU to perform some or all of processes and techniques described throughout this disclosure. In an embodiment, the PPU 700 is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In an embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by the PPU 700. In an embodiment, the PPU 700 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as a liquid crystal display (LCD) device. In an embodiment, the PPU 700 is utilized to perform computations such as linear algebra operations and machine-learning operations. FIG. 7 illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of processor architectures contemplated within the scope of this disclosure and that any suitable processor may be employed to supplement and/or substitute for the same.

In an embodiment, the PPU 700 comprises one or more arithmetic logic units (ALUs) configured to use weight information corresponding to a neural network, wherein weight information of at least a first one or more layers of the neural network is modified to compensate for deactivating one or more second layers of the neural network. In an embodiment, the PPU 700 is configured to group a set of filters based on alignment of the set of filters across two or more layers of a neural network; perform a regularization on the set of filters to enforce aligned structure sparsity across the two or more layers; determine, as a result of the regularization, whether the set of filters satisfy a pruning criteria; and remove the set of filters from the neural network. In an embodiment, the PPU 700 is further configured to determine that removal of the set of filters from the neural network does not affect the quality of predictions generated by the network (e.g., by validating it against a canonical training set and determining whether the accuracy of the model was affect and/or by how much). In an embodiment, the PPU 700 is further configured to validate that the quality of the neural network was substantially unaffected by removal of the set of layers by validating that the predication quality of the neural network did not decrease beyond a predetermined threshold.

In an embodiment, one or more PPUs are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In an embodiment, the PPU 700 is configured to accelerate deep learning systems and applications including the following non-limiting examples: autonomous vehicle platforms, deep learning, high-accuracy speech, image, text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and more.

In an embodiment, the PPU 700 includes an Input/Output (“I/O”) unit 706, a front-end unit 710, a scheduler unit 712, a work distribution unit 714, a hub 716, a crossbar (“Xbar”) 720, one or more general processing clusters (“GPCs”) 718, and one or more memory partition units 722. In an embodiment, the PPU 700 is connected to a host processor or other PPUs 700 via one or more high-speed GPU interconnects 708. In an embodiment, the PPU 700 is connected to a host processor or other peripheral devices via an interconnect 702. In an embodiment, the PPU 700 is connected to a local memory comprising one or more memory devices 704. In an embodiment, the local memory comprises one or more dynamic random access memory (“DRAM”) devices. In an embodiment, the one or more DRAM devices are configured and/or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device.

The high-speed GPU interconnect 708 may refer to a wire-based multi-lane communications link that is used by systems to scale and include one or more PPUs 700 combined with one or more CPUs, supports cache coherence between the PPUs 700 and CPUs, and CPU mastering. In an embodiment, data and/or commands are transmitted by the high-speed GPU interconnect 708 through the hub 716 to/from other units of the PPU 700 such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated in FIG. 7.

In an embodiment, the I/O unit 706 is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated in FIG. 7) over the system bus 702. In an embodiment, the I/O unit 706 communicates with the host processor directly via the system bus 702 or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit 706 may communicate with one or more other processors, such as one or more of the PPUs 700 via the system bus 702. In an embodiment, the I/O unit 706 implements a Peripheral Component Interconnect Express (“PCIe”) interface for communications over a PCIe bus. In an embodiment, the I/O unit 706 implements interfaces for communicating with external devices.

In an embodiment, the I/O unit 706 decodes packets received via the system bus 702. In an embodiment, at least some packets represent commands configured to cause the PPU 700 to perform various operations. In an embodiment, the I/O unit 706 transmits the decoded commands to various other units of the PPU 700 as specified by the commands. In an embodiment, commands are transmitted to the front-end unit 710 and/or transmitted to the hub 716 or other units of the PPU 700 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated in FIG. 7). In an embodiment, the I/O unit 706 is configured to route communications between and among the various logical units of the PPU 700.

In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 700 for processing. In an embodiment, a workload comprises instructions and data to be processed by those instructions. In an embodiment, the buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the PPU 700—the host interface unit may be configured to access the buffer in a system memory connected to the system bus 702 via memory requests transmitted over the system bus 702 by the I/O unit 706. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 700 such that the front-end unit 710 receives pointers to one or more command streams and manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 700.

In an embodiment, the front-end unit 710 is coupled to a scheduler unit 712 that configures the various GPCs 718 to process tasks defined by the one or more streams. In an embodiment, the scheduler unit 712 is configured to track state information related to the various tasks managed by the scheduler unit 712 where the state information may indicate which GPC 718 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. In an embodiment, the scheduler unit 712 manages the execution of a plurality of tasks on the one or more GPCs 718.

In an embodiment, the scheduler unit 712 is coupled to a work distribution unit 714 that is configured to dispatch tasks for execution on the GPCs 718. In an embodiment, the work distribution unit 714 tracks a number of scheduled tasks received from the scheduler unit 712 and the work distribution unit 714 manages a pending task pool and an active task pool for each of the GPCs 718. In an embodiment, the pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC 718; the active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs 718 such that as a GPC 718 completes the execution of a task, that task is evicted from the active task pool for the GPC 718 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 718. In an embodiment, if an active task is idle on the GPC 718, such as while waiting for a data dependency to be resolved, then the active task is evicted from the GPC 718 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC 718.

In an embodiment, the work distribution unit 714 communicates with the one or more GPCs 718 via XBar 720. In an embodiment, the XBar 720 is an interconnect network that couples many of the units of the PPU 700 to other units of the PPU 700 and can be configured to couple the work distribution unit 714 to a particular GPC 718. Although not shown explicitly, one or more other units of the PPU 700 may also be connected to the XBar 720 via the hub 716.

The tasks are managed by the scheduler unit 712 and dispatched to a GPC 718 by the work distribution unit 714. The GPC 718 is configured to process the task and generate results. The results may be consumed by other tasks within the GPC 718, routed to a different GPC 718 via the XBar 720, or stored in the memory 704. The results can be written to the memory 704 via the memory partition units 722, which implement a memory interface for reading and writing data to/from the memory 704. The results can be transmitted to another PPU or CPU via the high-speed GPU interconnect 708. In an embodiment, the PPU 700 includes a number U of memory partition units 722 that is equal to the number of separate and distinct memory devices 704 coupled to the PPU 700. A memory partition unit 722 will be described in more detail below in conjunction with FIG. 9.

In an embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 700. In an embodiment, multiple compute applications are simultaneously executed by the PPU 700 and the PPU 700 provides isolation, quality of service (“QoS”), and independent address spaces for the multiple compute applications. In an embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 700 and the driver kernel outputs tasks to one or more streams being processed by the PPU 700. In an embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp. In an embodiment, a warp comprises a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In an embodiment, cooperating threads can refer to a plurality of threads including instructions to perform the task and that exchange data through shared memory. Threads and cooperating threads are described in more detail, in accordance with one embodiment, in conjunction with FIG. 9.

FIG. 8 illustrates a GPC 800 such as the GPC illustrated of the PPU 700 of FIG. 7, in accordance with one embodiment. In an embodiment, each GPC 800 includes a number of hardware units for processing tasks and each GPC 800 includes a pipeline manager 802, a pre-raster operations unit (“PROP”) 804, a raster engine 808, a work distribution crossbar (“WDX”) 816, a memory management unit (“MMU”) 818, one or more Data Processing Clusters (“DPCs”) 806, and any suitable combination of parts. It will be appreciated that the GPC 800 of FIG. 8 may include other hardware units in lieu of or in addition to the units shown in FIG. 8.

In an embodiment, the operation of the GPC 800 is controlled by the pipeline manager 802. The pipeline manager 802 manages the configuration of the one or more DPCs 806 for processing tasks allocated to the GPC 800. In an embodiment, the pipeline manager 802 configures at least one of the one or more DPCs 806 to implement at least a portion of a graphics rendering pipeline. In an embodiment, a DPC 806 is configured to execute a vertex shader program on the programmable streaming multiprocessor (“SM”) 814. The pipeline manager 802 is configured to route packets received from a work distribution to the appropriate logical units within the GPC 800, in an embodiment, and some packets may be routed to fixed function hardware units in the PROP 804 and/or raster engine 808 while other packets may be routed to the DPCs 806 for processing by the primitive engine 812 or the SM 814. In an embodiment, the pipeline manager 802 configures at least one of the one or more DPCs 806 to implement a neural network model and/or a computing pipeline.

The PROP unit 804 is configured, in an embodiment, to route data generated by the raster engine 808 and the DPCs 806 to a Raster Operations (“ROP”) unit in the memory partition unit, described in more detail above. In an embodiment, the PROP unit 804 is configured to perform optimizations for color blending, organize pixel data, perform address translations, and more. The raster engine 808 includes a number of fixed function hardware units configured to perform various raster operations, in an embodiment, and the raster engine 808 includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. The setup engine, in an embodiment, receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for the primitive; the output of the coarse raster engine is transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. In an embodiment, the fragments that survive clipping and culling are passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. In an embodiment, the output of the raster engine 808 comprises fragments to be processed by any suitable entity such as by a fragment shader implemented within a DPC 806.

In an embodiment, each DPC 806 included in the GPC 800 comprises an M-Pipe Controller (“MPC”) 810; a primitive engine 812; one or more SMs 814; and any suitable combination thereof. In an embodiment, the MPC 810 controls the operation of the DPC 806, routing packets received from the pipeline manager 802 to the appropriate units in the DPC 806. In an embodiment, packets associated with a vertex are routed to the primitive engine 812, which is configured to fetch vertex attributes associated with the vertex from memory; in contrast, packets associated with a shader program may be transmitted to the SM 814.

In an embodiment, the SM 814 comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. In an embodiment, the SM 814 is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In an embodiment, all threads in the group of threads execute the same instructions. In an embodiment, the SM 814 implements a SIMT (Single-Instruction, Multiple Thread) architecture wherein each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. In an embodiment, execution state is maintained for each individual thread and threads executing the same instructions may be converged and executed in parallel for better efficiency. In an embodiment, the SM 814 is described in more detail below.

In an embodiment, the MMU 818 provides an interface between the GPC 800 and the memory partition unit and the MMU 818 provides translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the MMU 818 provides one or more translation lookaside buffers (“TLBs”) for performing translation of virtual addresses into physical addresses in memory.

FIG. 9 illustrates a memory partition unit of a PPU, in accordance with one embodiment. In an embodiment, the memory partition unit 900 includes a Raster Operations (“ROP”) unit 902; a level two (“L2”) cache 904; a memory interface 906; and any suitable combination thereof. The memory interface 906 is coupled to the memory. Memory interface 906 may implement 32, 64, 128, 1124-bit data buses, or the like, for high-speed data transfer. In an embodiment, the PPU incorporates U memory interfaces 906, one memory interface 906 per pair of partition units 900, where each pair of partition units 900 is connected to a corresponding memory device. For example, PPU may be connected to up to Y memory devices, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory (“GDDR5 SDRAM”).

In an embodiment, the memory interface 906 implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the PPU, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1124 bits.

In an embodiment, the memory supports Single-Error Correcting Double-Error Detecting (“SECDED”) Error Correction Code (“ECC”) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where PPUs process very large datasets and/or run applications for extended periods.

In an embodiment, the PPU implements a multi-level memory hierarchy. In an embodiment, the memory partition unit 900 supports a unified memory to provide a single unified virtual address space for CPU and PPU memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a PPU to memory located on other processors is trace to ensure that memory pages are moved to the physical memory of the PPU that is accessing the pages more frequently. In an embodiment, the high-speed GPU interconnect 708 supports address translation services allowing the PPU to directly access a CPU's page tables and providing full access to CPU memory by the PPU.

In an embodiment, copy engines transfer data between multiple PPUs or between PPUs and CPUs. In an embodiment, the copy engines can generate page faults for addresses that are not mapped into the page tables and the memory partition unit 900 then services the page faults, mapping the addresses into the page table, after which the copy engine performs the transfer. In an embodiment, memory is pinned (i.e., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. In an embodiment, with hardware page faulting, addresses can be passed to the copy engines without regard as to whether the memory pages are resident, and the copy process is transparent.

Data from the memory of FIG. 7 or other system memory is fetched by the memory partition unit 900 and stored in the L2 cache 904, which is located on-chip and is shared between the various GPCs, in accordance with one embodiment. Each memory partition unit 900, in an embodiment, includes at least a portion of the L2 cache 770 associated with a corresponding memory device. In an embodiment, lower level caches are implemented in various units within the GPCs. In an embodiment, each of the SMs 840 may implement a level one (“L1”) cache wherein the L1 cache is private memory that is dedicated to a particular SM 840 and data from the L2 cache 904 is fetched and stored in each of the L1 caches for processing in the functional units of the SMs 840. In an embodiment, the L2 cache 904 is coupled to the memory interface 906 and the XBar 720.

The ROP unit 902 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and more, in an embodiment. The ROP unit 902, in an embodiment, implements depth testing in conjunction with the raster engine, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine. In an embodiment, the depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. In an embodiment, if the fragment passes the depth test for the sample location, then the ROP unit 902 updates the depth buffer and transmits a result of the depth test to the raster engine. It will be appreciated that the number of partition units 900 may be different than the number of GPCs and, therefore, each ROP unit 902 can, in an embodiment, be coupled to each of the GPCs. In an embodiment, the ROP unit 902 tracks packets received from the different GPCs and determines which that a result generated by the ROP unit 902 is routed to through the Xbar.

FIG. 10 illustrates a streaming multi-processor such as the streaming multi-processor of FIG. 8, in accordance with one embodiment. In an embodiment, the SM 1000 includes: an instruction cache 1002; one or more scheduler units 1004; a register file 1008; one or more processing cores 1010; one or more special function units (“SFUs”) 1012; one or more load/store units (“LSUs”) 1014; an interconnect network 1016; a shared memory/L1 cache 1018; and any suitable combination thereof. In an embodiment, the work distribution unit dispatches tasks for execution on the GPCs of the PPU and each task is allocated to a particular DPC within a GPC and, if the task is associated with a shader program, the task is allocated to an SM 1000. In an embodiment, the scheduler unit 1004 receives the tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SM 1000. In an embodiment, the scheduler unit 1004 schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In an embodiment, each warp executes threads. In an embodiment, the scheduler unit 1004 manages a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (e.g., cores 1010, SFUs 1012, and LSUs 1014) during each clock cycle.

In an embodiment, the SM 1000 comprising one or more processors (e.g., the one or more processing cores 1010) and memory (e.g., implemented at least in part using the instruction cache 1002) that includes instructions which, if executed by the one or more processors, causes the SM 1000 to use weight information corresponding to a neural network, wherein weight information of at least a first one or more layers of the neural network is modified to compensate for deactivating one or more second layers of the neural network. In an embodiment, the SM 1000 is configured with computer-readable instructions which, as a result of execution, cause the SM 1000 identify a group of filters of two or more layers of a neural network that are to be removed together; applying a regularization to the group of filters to improve sparsity across the group of filters; determine that, as a result of applying the regularization, that the group of filters is sufficiently sparse to be removed; and remove the group of filters from the neural network. In an embodiment, the weights of the neural network are re-organized according to a group lasso regularization such that quality (e.g., accuracy) of the neural network is substantially unaffected by the removal of the group of filters, as the weights of the group of filters are small enough that they do not affect or do not meaningfully affect predictions of the neural network. In an embodiment, the SM 1000 determines that a first filter is to be removed along with a second filter because both filters are share a common index placement (e.g., both are the i-th filter of two layers that are connected by element-wise operations and are to be removed simultaneously).

Cooperative Groups may refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer, more efficient parallel decompositions. In an embodiment, cooperative launch APIs support synchronization amongst thread blocks for the execution of parallel algorithms. In an embodiment, applications of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads( ) function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (i.e., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on the threads in a cooperative group. The programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

In an embodiment, a dispatch unit 1006 is configured to transmit instructions to one or more of the functional units and the scheduler unit 1004 includes two dispatch units 1006 that enable two different instructions from the same warp to be dispatched during each clock cycle. In an embodiment, each scheduler unit 1004 includes a single dispatch unit 1006 or additional dispatch units 1006.

Each SM 1000, in an embodiment, includes a register file 1008 that provides a set of registers for the functional units of the SM 1000. In an embodiment, the register file 1008 is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 1008. In an embodiment, the register file 1008 is divided between the different warps being executed by the SM 1000 and the register file 1008 provides temporary storage for operands connected to the data paths of the functional units. In an embodiment, each SM 1000 comprises a plurality of L processing cores 1010. In an embodiment, the SM 1000 includes a large number (e.g., 128 or more) of distinct processing cores 1010. Each core 1010, in an embodiment, includes a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the cores 1010 include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores are configured to perform matrix operations in accordance with an embodiment. In an embodiment, one or more tensor cores are included in the cores 1010. In an embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In an embodiment, the tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In an embodiment, the 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. Tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements, in an embodiment. In an embodiment, an API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In an embodiment, at the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.

In an embodiment, each SM 1000 comprises M SFUs 1012 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the SFUs 1012 include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the SFUs 1012 include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM 1000. In an embodiment, the texture maps are stored in the shared memory/L1 cache. The texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail), in accordance with one embodiment. In an embodiment, each SM 1000 includes two texture units.

Each SM 1000 comprises N LSUs 854 that implement load and store operations between the shared memory/L1 cache 906 and the register file 1008, in an embodiment. Each SM 1000 includes an interconnect network 1016 that connects each of the functional units to the register file 1008 and the LSU 1014 to the register file 1008, shared memory/L1 cache 1018 in an embodiment. In an embodiment, the interconnect network 1016 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 1008 and connect the LSUs 1014 to the register file and memory locations in shared memory/L1 cache 1018.

The shared memory/L1 cache 1018 is an array of on-chip memory that allows for data storage and communication between the SM 1000 and the primitive engine and between threads in the SM 1000 in an embodiment. In an embodiment, the shared memory/L1 cache 1018 comprises 128 KB of storage capacity and is in the path from the SM 1000 to the partition unit. The shared memory/L1 cache 1018, in an embodiment, is used to cache reads and writes. One or more of the shared memory/L1 cache 1018, L2 cache, and memory are backing stores.

Combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses, in an embodiment. The capacity, in an embodiment, is used or is usable as a cache by programs that do not use shared memory, such as if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache 1018 enables the shared memory/L1 cache 1018 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data, in accordance with an embodiment. When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. In an embodiment, fixed function graphics processing units are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit assigns and distributes blocks of threads directly to the DPCs, in an embodiment. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM 1000 to execute the program and perform calculations, shared memory/L1 cache 1018 to communicate between threads, and the LSU 1014 to read and write global memory through the shared memory/L1 cache 1018 and the memory partition unit, in accordance with one embodiment. In an embodiment, when configured for general purpose parallel computation, the SM 1000 writes commands that the scheduler unit can use to launch new work on the DPCs.

In an embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and more. In an embodiment, the PPU is embodied on a single semiconductor substrate. In an embodiment, the PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices such as additional PPUs, the memory, a reduced instruction set computer (“RISC”) CPU, a memory management unit (“MMU”), a digital-to-analog converter (“DAC”), and the like.

In an embodiment, the PPU may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU may be an integrate graphics processing unit (“iGPU”) included in the chipset of the motherboard.

FIG. 11 illustrates a computer system 1100 in which the various architecture and/or functionality can be implemented, in accordance with one embodiment. The computer system 1100, in an embodiment, is configured to implement various processes and methods described throughout this disclosure.

In an embodiment, the computer system 1100 comprises at least one central processing unit 1102 that is connected to a communication bus 1110 implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). In an embodiment, the computer system 1100 includes a main memory 1104 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in the main memory 1104 which may take the form of random access memory (“RAM”). In an embodiment, a network interface subsystem 1122 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems from the computer system 1100.

The computer system 1100, in an embodiment, includes input devices 1108, the parallel processing system 1112, and display devices 1106 which can be implemented using a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display, or other suitable display technologies. In an embodiment, user input is received from input devices 1108 such as keyboard, mouse, touchpad, microphone, and more. In an embodiment, each of the foregoing modules can be situated on a single semiconductor platform to form a processing system.

In the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (“CPU”) and bus implementation. Of course, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.

In an embodiment, computer programs in the form of machine-readable executable code or computer control logic algorithms are stored in the main memory 1104 and/or secondary storage. Computer programs, if executed by one or more processors, enable the system 1100 to perform various functions in accordance with one embodiment. The memory 1104, the storage, and/or any other storage are possible examples of computer-readable media. Secondary storage may refer to any suitable storage device or system such as a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (“DVD”) drive, recording device, universal serial bus (“USB”) flash memory.

In an embodiment, the architecture and/or functionality of the various previous figures are implemented in the context of the central processor 1102; parallel processing system 1112; an integrated circuit capable of at least a portion of the capabilities of both the central processor 1102; the parallel processing system 1112; a chipset (e.g., a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.); and any suitable combination of integrated circuit.

In an embodiment, the architecture and/or functionality of the various previous figures is be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and more. In an embodiment, the computer system 1100 may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.

In an embodiment, a parallel processing system 1112 includes a plurality of PPUs 1114 and associated memories 1116. In an embodiment, the PPUs are connected to a host processor or other peripheral devices via an interconnect 1118 and a switch 1120 or multiplexer. In an embodiment, the parallel processing system 1112 distributes computational tasks across the PPUs 1114 which can be parallelizable—for example, as part of the distribution of computational tasks across multiple GPU thread blocks. In an embodiment, memory is shared and accessible (e.g., for read and/or write access) across some or all of the PPUs 1114, although such shared memory may incur performance penalties relative to the use of local memory and registers resident to a PPU. In an embodiment, the operation of the PPUs 1114 is synchronized through the use of a command such as _syncthreads( ) which requires all threads in a block (e.g., executed across multiple PPUs 1114) to reach a certain point of execution of code before proceeding.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the invention as set forth in the claims.

Other variations are within the spirit of the present disclosure. Thus, while the disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the invention to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the invention, as defined in the appended claims.

The use of the terms “a” and “an” and “the” and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. The term “connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein and each separate value is incorporated into the specification as if it were individually recited herein. The use of the term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, the term “subset” of a corresponding set does not necessarily denote a proper subset of the corresponding set, but the subset and the corresponding set may be equal.