SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE TOTAL POWER WITHIN A CIRCUIT DESIGN | Patent Application Number 14221355

14221355
Not Appealed
Patent Number-
Publication NumberUS 20150269304 A1
Filled DateMar 21, 2014
Priority DateMar 21, 2014
Inventor/Applicants
ExaminesLIN, SUN J
Art Unit2851
Technology Center2800
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