CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of co-pending application Ser. No. 11/050,963, filed on Feb. 7, 2005, the entire contents of which are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. Â§ 120.

BACKGROUND OF THE INVENTION

The invention relates to a method of semiconductor manufacturing process, and more particularly to a method of forming a silicon tip by a single etching process, which can be used to form a tip floating gate to increase erase speed.

Flash memory, which has the advantages of nonvolatility, high density, low power consumption, and low cost, has become a major product of the semiconductor industry.

Flash memory, which comprises a control gate used to apply operating voltage and a floating gate used to store charges, performs program or erase operations by applying different voltages of the control gate, source, and drain to move charges on and off the floating gate.

When the edge of the floating gate is a tip, the electrical field is easily concentrated, and the point is easily discharged. If the point discharge is increased, the erasing effect is strong.

U.S. Pat. No. 6,759,300 discloses a method for fabricating a multi-tip floating gate by an anisotropic etching process with gases comprising CF4, CHF3, or a combination thereof, and the tip angle can be controlled by the angle of the anisotropic etching process.

SUMMARY OF THE INVENTION

The invention provides a method of forming a silicon tip without bottom dimple by a single etching process.

The invention also provides a method of forming a tip floating gate by a single etching process to increase erase speed of flash memory devices.

To achieve these and other advantages, the invention comprises: providing a substrate having a silicon layer; putting the substrate into an etching chamber of an etching process tool; and etching the silicon layer to form a tip silicon without bottom dimple by an etching gas comprising (1) chlorine and/or (2) oxygen/helium.

In addition, the invention may further control the tip silicon angles by adjusting the etching parameters of the etching gas compositions and ratios, the etching chamber pressures, and the etching process tool radio frequency (RF) powers.

The invention controls the tip silicon angles easily by adjusting the above etching parameters, which has a simple process not requiring additional process steps, and improves the bottom dimple problem.

Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and in which:

FIGS. 1A and 1B are substrates suitable for the invention;

FIG. 2 shows tip angle Î¸ and bottom dimple d;

FIGS. 3A through 3F are cross-sections showing an embodiment of forming a tip floating gate according to the invention; and

FIGS. 4A through 4F are cross-sections showing another embodiment of forming a tip floating gate according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

First, a substrate having a silicon layer 104 is provided. The silicon layer 104 may be laid in a trench 102, as shown in FIG. 1A, or disposed under a patterned mask layer 112 with an opening, as shown in FIG. 1B. The silicon layer 104 may comprise polysilicon, epitaxial silicon, single crystal silicon, or doped silicon.

The invention employs hydrogen bromide (HBr) as a major etching gas in an etcher, such as a transformer-coupled plasma (TCP) etching tool, with suitable amounts of gases (1) chlorine and/or (2) oxygen/helium to form a tip angle Î¸ of the above silicon layer 104 without bottom dimple d. The tip angle Î¸ and bottom dimple d are depicted in FIG. 2. The invention may further control the tip angle Î¸ by adjusting the etching parameters of etching gas compositions and ratios, chamber pressures, and radio frequency (RF) powers.

Below are some examples of the invention, which control the tip angle Î¸ of the silicon layer 104 shown in FIG. 1A, and the silicon layer 104 is polysilicon.

EXAMPLE 1 Effects of Hydrogen Bromide Contents to Polysilicon Tip Angles and Bottom Dimple Depths

The top and bottom RF powers of the etching process tool are 600 and 20 watts respectively, the temperature of the bottom RF electrode is 50Â° C., and the distance between the substrate and the top RF electrode is 5.5 centimeters. Etching gases comprise 20 sccm of chlorine (Cl₂), 150 sccm of helium (He), with 50 sccm and 150 sccm of hydrogen bromide (HBr) individually, such that the hydrogen bromide contents are 22.7% and 46.8% respectively. The etching chamber pressure is about 6 mTorr.

Table 1 shows that etching the polysilicon layer by the above 22.7% and 46.8% of hydrogen bromide obtains tip angles Î¸ 55.1Â° and 45.6Â° with bottom dimple depths d 320 â„« and 480 â„« respectively. Table 1 illustrates that while the hydrogen bromide contents increase, the tip angles of polysilicon decrease, and the bottom dimple problem worsens.

TABLE 1parametersresultsHBrHBrCl₂HeRF powersChamberAngleDimple(%)(sccm)(sccm)(sccm)top/bottom(W)pressure(mTorr)(Â°)(â„«)22.75020150600/20655.132046.815020150600/20645.6480

EXAMPLE 2 Effects of Etching Chamber Pressures to Polysilicon Tip Angles and Bottom Dimple Depths

The top and bottom RF powers of the etching process tool are 600 and 20 watts respectively, the temperature of the bottom RF electrode is 50Â° C., and the distance between the substrate and the top RF electrode is 5.5 centimeters. Etching gases comprise 20 sccm of chlorine, 100 sccm of helium, and 50 sccm of hydrogen bromide. The etching chamber pressures are about 6 and 10 mTorr individually.

Table 2 shows that etching the polysilicon layer by the above 6 mTorr and 10 mTorr of etching chamber pressures obtains tip angles Î¸ 45.7Â° and 36.8Â° with bottom dimple depths d 510 â„« and 810 â„« respectively. Table 2 illustrates that while the etching chamber pressures increase, the tip angles of polysilicon decrease, and the bottom dimple problem becomes worse.

TABLE 2parametersresultsChamberHBrHBrCl₂HeRF powersAngleDimplepressure(mTorr)(%)(sccm)(sccm)(sccm)top/bottom(W)(Â°)(â„«)629.45020100600/2045.75101029.45020100600/2036.8810

EXAMPLE 3 Effects of RF Powers to Polysilicon Tip Angles and Bottom Dimple Depths

The top RF power of the etching process tool is 600 watts, and the bottom RF powers are 10 and 20 watts respectively. The temperature of the bottom RF electrode is 50Â° C., and the distance between the substrate and the top RF electrode is 5.5 centimeters. Etching gas comprises 110 sccm of chlorine. The etching chamber pressure is about 4.5 mTorr.

Table 3 shows that etching the polysilicon layer by the above 10 and 20 watts of the bottom RF powers obtains tip angles Î¸ 65.3Â° and 61.1Â° with bottom dimple depths d 470 â„« and 880 â„« respectively. Table 2 illustrates that while the bottom RF powers increase, the ion bombardment effects are enhanced, which increase the etching rates, but cause the bottom dimple problem more significantly.

TABLE 3parametersresultsRF powersChamberHBrAngleDimpletop/bottom(W)pressure(mTorr)(sccm)(Â°)(â„«)600/104.511065.3470600/204.511061.1880

EXAMPLE 4 Effects of Chlorine and Oxygen/Helium to Polysilicon Tip Angles and Bottom Dimple Depths

The top and bottom RF powers of the etching process tool are 600 and 20 watts respectively, the temperature of the bottom RF electrode is 50Â° C., and the distance between the substrate and the top RF electrode is 5.5 centimeters. The etching chamber pressure is about 10 mTorr. Etching gases comprise 200 sccm of hydrogen bromide with 20 sccm of chlorine, and 110 sccm of hydrogen bromide with 18 sccm of a mixture gas oxygen(O₂)/helium respectively. The ratio of oxygen to helium of the mixture gas is about 3:7.

Table 4 shows that etching the polysilicon layer by the above chlorine-containing and oxygen/helium-containing etching gases obtains tip angles Î¸ 67.4Â° and 58.4Â° respectively without bottom dimple. The etching gas with a small amount of chlorine helps the polysilicon to obtain a more level bottom surface, while the etching gas with a few amount of oxygen/helium mixture gas enhances the etching rate of the polysilicon layer.

TABLE 4parametersresultsCl₂He/O₂(7/3)HBrRF powersPressureAngleDimpleGas(%)(sccm)(sccm)(sccm)top/bottom(W)(mTorr)(Â°)(â„«)Cl₂11%20â€”200600/201067.4NoHeâ€”O₂14%â€”18110600/201058.4No

It is confirmed by the above examples that the etching parameters of etching gas compositions and ratios, chamber pressures, and RF powers affect the tip angles of polysilicon.

After adjusting the etching parameters such as shown in Table 5, tip angles of 77.5Â°, 55.4Â°, and 28.5Â° without bottom dimple individually are obtained.

TABLE 5parametersresultsHeâ€”O2(7:3)Cl₂HBrRF powersPressureAngleDimple(sccm)(sccm)(sccm)top/bottom(W)(mTorr)(Â°)(â„«)1030110250/30677.4No152070250/20655.4No1030110600/20628.5No

Accordingly, it is concluded from the above results that we may obtain a specific tip angle of polysilicon by adjusting etching parameters summarized as below, wherein the etching chamber pressure is below 8 mTorr, the temperature of the bottom RF electrode is 50Â° C., and the distance between the substrate and the top RF electrode is 5.5 centimeters.

(A) silicon tip angles of 65Ëœ85 degrees

1. Etching gas comprises 65Ëœ80% of hydrogen bromide, 15Ëœ25% of chlorine, and 5Ëœ8% of oxygen/helium, wherein the ratio of oxygen to helium is about 3:7.

2. The flow rate of the etching gas is about 132Ëœ166 sccm.

3. The top RF power of the etching process tool is about 225Ëœ275 watts, and the bottom RF power is about 25Ëœ35 watts.

(B) silicon tip angles of 45Ëœ65 degrees:

1. Etching gas comprises 61Ëœ71% of hydrogen bromide, 14Ëœ24% of chlorine, and 12Ëœ16% of oxygen/helium, wherein the ratio of oxygen to helium is about 3:7.

2. The flow rate of the etching gas is about 91Ëœ116 sccm.

3. The top RF power of the etching process tool is about 225Ëœ275 watts, and the bottom RF power is about 15Ëœ35 watts.

(C) silicon tip angles of 15Ëœ45 degrees

1. Etching gas comprises 65Ëœ80% of hydrogen bromide, 15Ëœ25% of chlorine, and 5Ëœ8% of oxygen/helium, wherein the ratio of oxygen to helium is about 3:7.

2. The flow rate of the etching gas is about 132Ëœ166 sccm.

3. The top RF power of the etching process tool is about 300Ëœ600 watts, and the bottom RF power is about 15Ëœ35 watts.

The invention provides a method of forming a silicon tip by a single etching process, which may further control the tip angles by adjusting the etching parameters of gas compositions and ratios, chamber pressures, and RF powers. In addition, the invention also provides a method of forming a tip floating gate to increase erase speed.

A preferred embodiment of the invention is now described with reference to FIGS. 3A through 3F, which illustrate forming a tip floating gate, as well as how the tip angles may be adjusted according to the invention.

In FIG. 3A, a substrate 300 is provided. A gate dielectric layer 302 such as an oxide layer, and a first dielectric layer 304 such as a silicon nitride layer with trench 306 therein on the substrate 300 is then formed. The trench 306 exposes the top surface of the gate dielectric layer 302.

In FIG. 3B, a silicon layer 308 is deposited. The silicon layer 308 may be, but is not limited to, polysilicon, which can further comprise epitaxial silicon, single crystal silicon, or doped silicon.

Next, a CMP process is performed to remove the silicon layer 308 until the top surface of the first dielectric layer 304 is exposed, and/or an etch-back process to remove the silicon layer 308 to a level below the top surface of the first dielectric layer 304 in the trench 306. The first dielectric layer 304 may preferably have a high etch and/or polish selectivities relative to the silicon layer 308.

As shown in FIG. 3C, the above polished or etched silicon layer 308â€² may be at a level close to or below the top surface of the first dielectric layer 304.

Then, etching the silicon layer 308â€² to become a silicon layer 308â€³ having a tip 312 without the described bottom dimple problem, as shown in FIG. 3D. The silicon layer 308â€³ will be formed as a floating gate in subsequent processes, and the tip 312 angles may be controlled by the invention. Next, a second dielectric layer 310 such as an oxide is deposited, which may preferably have a high etch selectivity relative to the first dielectric layer 304.

In FIG. 3E, performing a CMP process to remove the second dielectric layer 310 until the top surface of the first dielectric layer 304 is exposed, or further polishing the dielectric layer 310 and 304 to form the first dielectric layer 304â€² and second dielectric layer 310â€², which are preferably above the silicon tip 312.

Next, the first dielectric layer 304â€² is removed to form a structure such as shown in FIG. 3F, wherein the silicon layer 308â€³ with the tip 312 acts as a floating gate, and the tip 312 angles may be controlled by adjusting the above etching parameters according to the invention. Etching gases comprising (1) chlorine and/or (2) oxygen/helium avoid the described bottom dimple problem.

Another embodiment of the invention is described with reference to FIGS. 4A through 4F, which illustrate forming a tip floating gate, as well as how the tip angles may be adjusted according to the invention.

In FIG. 4A, a substrate 400 is provided. A gate dielectric layer 402, a silicon layer 404, and a patterned mask layer 410 with an opening 412 are subsequently formed on the substrate 400, wherein the opening 412 exposes the top surface of the silicon layer 404. The gate dielectric layer 402 may be an oxide, and the silicon layer 404 may be, but is not limited to, polysilicon, which may further comprise epitaxial silicon, single crystal silicon, or doped silicon. The patterned mask layer 410 may comprise an etch mask 408 such as a photoresist layer, and an optional insulating layer 406 such as a silicon nitride disposed between the silicon layer 404 and the etch mask 408.

In FIG. 4B, etching the silicon layer 404 to become a silicon layer 404â€² having a rounded-corner 414 without a bottom dimple by the invention.

Removing the etch mask 408, as shown in FIG. 4C. Next, depositing a first dielectric layer 416 to fill the trench 412â€², as shown in FIG. 4D. The first dielectric layer 416 may comprise an oxide layer or fluorinated silicate glass (FSG) layer, which may preferably have a high etch and/or polish selectivities relative to the silicon layer 404 and insulating layer 406.

The first dielectric layer 416 is then planarized down to the top surface of the insulating layer 406, leaving a residual first dielectric layer 416â€², as shown in FIG. 4E.

Removing the insulating layer 406 to expose the silicon layer 404â€², followed by anisotropically etching the exposed silicon layer 404â€² using the residual first dielectric layer 416â€² as an etching mask, forming a silicon layer 404â€³ to serve as a floating gate, as shown in FIG. 4F. The tip angle 414â€² of the silicon layer 404â€³ may be controlled by the invention. In addition, etching gases comprising (1) chlorine and/or (2) oxygen/helium avoid bottom dimple problem.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.