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Bruce H Hess

Examiner (ID: 2600, Phone: (571)272-1525 , Office: P/1785 )

Most Active Art Unit
1774
Art Unit(s)
1513, 1605, 1504, 1785, 1794, 1508, 1774, 1317, 1509, 1604
Total Applications
4168
Issued Applications
3684
Pending Applications
26
Abandoned Applications
383

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4171164 [patent_doc_number] => 06125407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'System for flushing high-speed serial link buffers by ignoring received data and using specially formatted requests and responses to identify potential failure' [patent_app_type] => 1 [patent_app_number] => 9/123993 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125407.pdf [firstpage_image] =>[orig_patent_app_number] => 123993 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123993
System for flushing high-speed serial link buffers by ignoring received data and using specially formatted requests and responses to identify potential failure Jul 28, 1998 Issued
Array ( [id] => 4176808 [patent_doc_number] => 06105082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Data processor used in a data transfer system which includes a detection circuit for detecting whether processor uses bus in a forthcoming cycle' [patent_app_type] => 1 [patent_app_number] => 9/076755 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4552 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105082.pdf [firstpage_image] =>[orig_patent_app_number] => 076755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076755
Data processor used in a data transfer system which includes a detection circuit for detecting whether processor uses bus in a forthcoming cycle May 11, 1998 Issued
Array ( [id] => 4236123 [patent_doc_number] => 06041368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'System for operating input, processing and output units in parallel and using DMA circuit for successively transferring data through the three units via an internal memory' [patent_app_type] => 1 [patent_app_number] => 9/053966 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15671 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041368.pdf [firstpage_image] =>[orig_patent_app_number] => 053966 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053966
System for operating input, processing and output units in parallel and using DMA circuit for successively transferring data through the three units via an internal memory Apr 1, 1998 Issued
Array ( [id] => 4117805 [patent_doc_number] => 06098122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method and apparatus for adaptively blocking outgoing communication requests and adjusting the blocking factor according to the volume of requests being received in an information handling system' [patent_app_type] => 1 [patent_app_number] => 9/049513 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098122.pdf [firstpage_image] =>[orig_patent_app_number] => 049513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049513
Method and apparatus for adaptively blocking outgoing communication requests and adjusting the blocking factor according to the volume of requests being received in an information handling system Mar 26, 1998 Issued
Array ( [id] => 4238628 [patent_doc_number] => 06088744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Multiport data buffer having multi level caching wherein each data port has a FIFO buffer coupled thereto' [patent_app_type] => 1 [patent_app_number] => 9/023837 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3537 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088744.pdf [firstpage_image] =>[orig_patent_app_number] => 023837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023837
Multiport data buffer having multi level caching wherein each data port has a FIFO buffer coupled thereto Feb 12, 1998 Issued
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