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Patexia seeks prior art for US Patent 5,991,545 (US ‘545) which allegedly describes a special instruction set architecture of a central processing unit (CPU) which tackles various problems accompanying the adoption of a fixed length instruction format having a smaller bit number (16 bits) than that of a data word length (32 bits).
Various instructions of an instruction set can be executed by the CPU, and
- the instructions have a fixed instruction length of a first bit length (16 bits)
- the instructions set includes conditional/unconditional branch instructions
- each of the branch instructions has an area comprising a displacement value
- the displacement area of the conditional branch instruction(s) has a different bit width from that of the unconditional branch instruction(s)
The CPU includes,
- an instruction memory
- stores instructions of an instruction set
- an instruction register
- coupled to the instruction memory
- fetches a one instruction that has a displacement/offset value
- decode means
- decode the fetched one instruction in the instruction register
- a program counter (PC)
- stores an address of the fetched one instruction
- an execution unit
- performs an operation of data, whose maximum word length is a second bit length (such as 32 bits)
- performs an operation for immediate data having a bit length of greater than first bit length (16 bits)
- receives data located at an address concatenated from the address stored at the PC with the displacement value
Further explanation on the present embodiment based on a specific setting
In processing a data word of 32 bits in length, multiple immediate values are utilized by the CPU, some of them may be smaller than the length of the 16 bit instruction, while others might be larger than 16 bits. Here is this embodiment, the length of an instruction is 16 bits.
Problem: The instruction has a fixed length of 16 bits, the length of data word is 32 bits, thus it’s not realistic and practical to expect all immediate values to be fitted in the length of an instruction since some of them will be larger than 16 bits.
Solution: Use the value of a register (such as the program counter, PC) plus the relative address (offset/displacement), so as to select immediate value of more than 16 bits length. For more detailed explanation, please find column 21, line 25 - 52 and figure 13 of US Patent 5,991,545 (US ‘545).
- +5 for references that are non-patent literature
- +5 for references published in a foreign language other than English
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|1||Was the reference filed or published before June 24th, 1991?||T/F|
|2||Does the reference describe a central processing unit (CPU) which can process instructions in an instruction set which has a fixed instruction length of a first bit length?||5|
|3||Does the CPU include an instruction in the instruction set which fetches an immediate value from a location calculated based on the Program Counter and an offset value contained in the instruction, where the immediate value has a bit width greater than the first bit length (fixed instruction length)?||25|
|4||Does the instruction set have at least one conditional branch instruction and at least one unconditional branch instruction, each with an area which comprises a displacement corresponding to a jumped address?||25|
|5||Does the displacement area of the conditional branch instruction(s) have a different bit width from that of the unconditional branch instruction(s)?||45|
This is a Prior Art Search contest aimed at determining if a patent idea was known and publicly available before a patent was filed.
This contest will close on Sunday, September 14th, 2014 at 11:59 PM PST.
Please review the Contest Rules. For more information on how to submit to this Contest type, please read the Intro to Prior Art Search page.
Please review the full list of known references.
- All work must be original and prepared by a single author
- Maximum of one entry per person allowed
- Maximum length of 1,500 words
- Entries must be in English
- Ideas should be clearly expressed at a college-educated, non-expert level
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- , Cache Organization to Maximize Fetch Bandwidth IBM Technical Disclosure Bulletin vol. 32 No. 2 Jul. 1989 pp. 62-64.
- , I860 Microprocessor Internal Architecture Microprocessors and Microsystems vol. 14 No. 12 Mar. 1990 pp. 89-96.
- Kohn et al. Session 3: Floating Point Processors WAM 3.6: A 1000000 Transistor Microprocessor ISSC 89 Wednesday Feb. 15 1989 pp. 53-55. ,
- M68000 16/32-Bit Microprocessor Programmer's Reference Manual 1984 pp. 72 77 and 80.
- Osborn et al. Osborne 16-Bit Microprocessor Handbook Includes 2900 Chip Slice Family Osborne/McGraw-Hill 1981 pp. 1-1 to 1-5; 1-24 to 1-33; 4-1 to 4-4; and 4-35 to 4-45.
- Osborne 16-bit Microprocessor Handbook 1981 pp. 7-30 to 7-38.
- Tabak D. RISC Systems 1990 pp. 49-71.