Patexia. Contest



Patent Known References

TypePatent CountryPatent Number
Patent JP H02134860
Patent WO 1995019642
Patent US 5579207
Patent US 5495394
Patent DE 19516487A
Patent DE 1981323U
Patent DE 1981624U
Patent DE 4314913A
Patent DE 4430812C1
Patent DE 4433846A1
Patent EP 0531723A1
Patent EP 0559366A1
Patent EP 0926726A1
Patent JP S63156348A
Patent JP S63213943A
Patent US 4924589
Patent US 4939568
Patent US 4954875
Patent US 5087585
Patent US 5104820
Patent US 5208178
Patent US 5244818
Patent US 5258318
Patent US 5270261
Patent US 5276338
Patent US 5324678
Patent US 5324687
Patent US 5380681
Patent US 5391257
Patent US 5426072
Patent US 5442236
Patent US 5476810
Patent US 5489554
Patent US 5563084
Patent US 5627106
Patent US 5767001
Patent US 5846879
Patent US 5851894
Patent US 5877034
Patent US 5902118
Patent US 6187652
Patent US 6294829

Published Known References

TypeTitle of NPL
Journal "Sailer Philip; Singhal Piyush; et al. ""Creating 3D circuits using transferred films"". IEEE Circuits and Devices. November 1997"
Journal Akasaka et al. Solid State Technology (Feb. 1989).
Journal "Akasaka Y. ""Three-Dimensional IC Trends"" Proceedings of the IEEE vol. 74 No. 12 Dec. 1986 pp. 1703-1714."
Journal "Hayashi Y. et al. ""Cumulatively Bonded IC (Cubic) Technology For 3D-IC Fabrication"" 8th International Workshop on Future Electron Devices Mar. 14-16 1990 pp. 85-88."
Journal "Kuhn Stefan A. et al. ""Interconnect Capacitances Crosstalk and Signal Delay in Vertically Integrated Circuits"" IDEM 95-249 10.3.1 Siemens AG Corporate R&D Institute for Integrated Cirusits Fraunhofer Institute for Solid State Technology."
Journal Tewksbury et al. IEEE Circuits and Devices Magazine (Sep.1989).